Semiconductor memory device having an improved sense amplifier arrangement

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of data lines;
• a plurality of memory cells;
• wherein
• each of the memory cells has a first and a second diffusion region, a floating gate and a control gate, and wherein the control gate is coupled to one of the word lines, whereas the first diffusion region is coupled to one of the data lines, said semiconductor memory device including:
• sense amplifiers for amplifying data supplied via the data lines and stored in each memory cell coupled to the selected word line and for outputting the amplified data;
• and
• select switch circuits for sequentially receiving select signals for use in sequentially supplying the data stored in the selected memory cell to the sense amplifier;
• further comprising data select circuits for selecting the output signal of each sense amplifier in response to an address signal;
• wherein the select switch circuit sequentially supplies data according to the select signal received to the sense amplifier and wherein the sense amplifiers sequentially amplify the data on the data lines and output the amplified data, and
• wherein the sense amplifiers are provided as those corresponding to the plurality of data lines.