Read write memory with negative feedback-controlled dummy memory circuit

A static random access memory comprising:

• a plurality of word lines for receiving a cell selection signal;
• a plurality of pairs of bit lines;
• a plurality of first load circuits connected to the bit lines of a respective one of the pairs of bit lines for applying a voltage source thereto;
• a plurality of arrays of first memory cells, said arrays corresponding respectively to said first load circuits, each of the first memory cells including a pair of coupling transistors having a control terminal connected to a word line and a current path connected between the bit lines of a respective one of said pairs, and a pair of inverters connected in anti-parallel relationship to each other between said coupling transistors, said coupling transistors of each of the arrays providing a path between the bit lines of said one pair and said inverters in response to said cell selection signal to cause said inverters to assume one of two binary states;
• a plurality of first amplifier means being connected respectively to said arrays of said first memory cells;
• a pair of dummy bit lines;
• a second dummy load circuit identical to each of the first load circuits and connected to the dummy bit lines for applying said voltage source thereto;
• a second dummy memory cell including a pair of coupling transistors having a control terminal connected to a bias source and a current path connected to the dummy bit line, and an inverter connected so said coupling transistor, said coupling transistor establishing a path between said dummy bit line and said inverter to cause the inverter to assume a predetermined binary state;
• second amplifier means connected to said second memory cell;
• and
• comparator means for generating an output voltage representative of a deviation of a voltage developed by said second amplifier means from a reference voltage and negatively feeding the output voltage back to each of said first load circuits and said second load circuit.

A memory comprising:

• a plurality of word lines for receiving a cell selection signal;
• a bit line;
• a first load circuit connected to the bit line for applying thereto a source voltage;
• an array of first memory cells, each including a coupling transistor having a control terminal connected to a word line and a current path connected to said bit line, and an inverter connected to said coupling transistor, said coupling transistor providing a path to said bit line and said inverter in response to said cell selection signal to cause said inverter to assume one of two binary states;
• first amplifier means connected to said array of first memory cells;
• a dummy bit line;
• a second dummy load circuit identical to the first load circuit and connected to the dummy bit line for applying said voltage source thereto;
• a second dummy memory cell including a coupling transistor having a control terminal connected to a bias source and a current path connected to said dummy bit line, and an inverter connected to said coupling transistor, said coupling transistor establishing a path between said dummy bit line and said inverter to cause said inverter to assume a predetermined binary state;
• second amplifier means connected to said second memory cell;
• and
• comparator means for generating an output voltage representative of a deviation of a voltage developed by said second amplifier means from a reference voltage and negatively feeding the output voltage back to said first and second load circuits.

A static random access memory comprising:

• a plurality of word lines for receiving a cell selection signal;
• a plurality of bit lines;
• a plurality of first load circuits connected to one of the bit lines for applying a voltage source thereto;
• a plurality of arrays of first memory cells, said arrays corresponding respectively to said first load circuits, each of the first memory cells including a transistor having a control terminal connected to a word line and a current path connected to one of the bit lines, and an inverter connected to said coupling transistor, said transistor of each of the arrays providing a path between one of the bit lines and said inverters in response to said cell selection signal to cause said inverters to assume one of two binary states;
• a plurality of first amplifier means being connected to said arrays of said first memory cells;
• a dummy bit line;
• a second dummy load circuit identical to each of the first load circuits and connected to the dummy bit line for applying said voltage source thereto;
• a second dummy memory cell including a coupling transistor having a control terminal connected to a bias source and a current path connected to the dummy bit line, and an inverter connected to said coupling transistor, said coupling transistor establishing a path between said dummy bit line and said inverter to cause the inverter to assume a predetermined binary state;
• second amplifier means connected to said second memory cell;
• and
• comparator means for generating an output voltage representative of a deviation of a voltage developed by said second amplifier means from a reference voltage and negatively feeding the output voltage back to each of said first load circuits and said second load circuit.