Method and apparatus for minimizing power-up crowbar current in a retargetable SRAM memory system

Abstract

A retargetable SRAM system includes several block storage units that include a plurality of addressably selectable SRAM core cells, with a block single ended bit line driver coupleable to the output of each block storage unit to enhance voltage slew rate. To promote retargetability, digital (rather than analog) sense amplifiers are provided per each data output port. To minimize power-up crowbar current, the input of each unselected block bit line driver is forced to a "1" or "0" state. AMOS transistor coupled between the input port of each block bit line driver and an upper or lower system power supply has its gate input lead coupled to receive the system block select signal (or its complement). A desired SRAM core cell is accessed by specifying its row, column, and block address. A row select signal causes the cell output to be coupled to the input of the associated block bit line driver. The block select signal, its complement, and column select signal cause the output of the associated block bit line driver to be coupled to the input of the digital sense amplifier for the specified data output. The same block select signal (or its complement) turns on the MOS transistor coupled to the input node of each unselected block bit line driver. In a system with SRAM core cells arrayed into 128 rows and 256 columns, partitioned into four block storage units of 32 rows each, crowbar current is thus minimized for the 3.times.256 or 768 unselected block bit line drivers.

Dependencies are inferred from the claim text.