US 5,473,560 A · Method of reading data and read-only memory circuit

Abstract

In a method of reading data comprising the steps of selecting a given column line and a bit line adjoining to the column line among a plurality of column lines (102-1.about.102-3) and bit lines (101-1, 101-2)based on column selection signals (Y.sub.1 .about.Y.sub.3), selecting a given row line among a plurality of row lines (103-1.about.103-n) based on row selection signals (X.sub.0 .about.X.sub.n) and reading out data which is stored in memory cells (104-01.about.104-n4) each of which is coupled to the given column line and the row line to the selected bit line, the given column line is set at a first potential level (a potential level supplied by a voltage regulator circuit 160) and almost at the same time the selected bit line is set at a second potential level (a potential level supplied by a sense amplifier circuit 150) which is lower than the first potential level and unselected column lines are set at a third potential level (ground potential level or a potential level supplied by the potential supply circuit 190) which is lower than the second potential level to read out data. As a result, it is possible to perform a high-speed data reading. Moreover, it is possible to realize low power consumption since there flows no useless current at a standby state.

Claims14

Dependent claims

A method of reading data comprising the steps of selecting a given column line and a bit line which adjoins to said column line among a plurality of column and bit lines in response to a column selection signal, selecting a given row line among a plurality of row lines in response to a row selection signal, and reading out data which is stored in a memory cell connected to said given column and row lines to said selected bit line;

characterized in that
data is read out from said memory cell by setting said given column line at a first potential level and almost at the same time setting said selected bit line at a second potential level which is lower than said first potential level and setting unselected column lines at a third potential level which is equal to or lower than said second potential level.

A read-only memory circuit comprising:

a plurality of column lines;
a plurality of bit lines arranged with said column lines in turns in parallel thereto;
a plurality of row lines arranged substantially at right angles to said bit and column lines;
a plurality of memory cells for storing data therein, each memory cell having a control terminal coupled to one of said row lines and being coupled between each column line and each bit line;
a row selection circuit for selecting a given row line among said plural row lines;
a column selection circuit for selecting a given column line among said plural column lines and a bit line which adjoins to said given column line to read out data which is stored in a memory cell connected to said given row and column lines to said selected bit line;
a first potential supply circuit for applying a first potential to said selected column line;
a second potential supply circuit for applying a second potential which is lower than said first potential to said selected bit line;
and
a third potential supply circuit for applying a third potential which is equal to or lower than said second potential to unselected column lines.

7 more elements

A read-only memory circuit characterized in comprising:

a first and a second column lines;
a first bit line arranged between said first and second column lines;
a first memory cell for storing a first data therein which is coupled between said first column line and said first bit line;
a second memory cell for storing a second data therein which is coupled between said second column line and said first bit line;
a column selection circuit which selects said first column line and said first bit line and supplies said first data to said first bit line based on the voltage between said first column line and said first bit line;
a first potential supply circuit for applying a first potential to said first column line;
a second potential supply circuit for applying a second potential which is lower than said first potential to said first bit line;
and
a third potential supply circuit for applying a third potential which is equal to or lower than said second potential to said second column line.

6 more elements

Dependencies are inferred from the claim text.

Method of reading data and read-only memory circuit

Life of this patent

Method of reading data and read-only memory circuit

Life of this patent

Abstract

Claims14