Hardware implemented multiplier

A multiplier performing multiplication of a first multi-bit binary number and a second multi-bit binary number, comprising:

• partial product generating means for generating a plurality of partial products from said first multi-bit binary number and said second multi-bit binary number and inverting a sign indicating positive and negative of a part of the partial products generated and non- inverting a sign of a remaining partial product, to generate final partial products, each said partial product being a non-redundant binary number produced from a signal generated according to a value of at least one digit of said first multi-bit binary number and said second multi-bit binary number;
• redundant binary number generating means for generating a plurality of multi-bit redundant binary numbers from said final partial products in such a manner that one multi-bit redundant binary number consists of one sign inverted partial product and one sign non-inverted partial product, in which a digit of said one multi-bit redundant binary number consists of a number at a corresponding digit of said one sign inverted partial product and a number at the corresponding digit of said one sign non-inverted partial product;
• redundant binary adding means for redundant binary adding said plurality of multi-bit redundant binary numbers to generate a final redundant binary number;
• and
• final product generation means for converting said finally generated multi-bit redundant binary number into an ordinary binary number code in which said first and second multi-bit binary numbers are represented to form a multi-bit binary number representing a product of said first multi-bit binary number and said second multi-bit binary number.