Apparatus and method of controlling paging unit of coprocessor built in display control system
AssigneeKabushiki Kaisha Toshiba
InventorAkihisa Fujimoto
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Abstract
A comparison result of a comparator in a paging unit determines whether the access target of a coprocessor is a system memory or a VRAM. If the target is a VRAM, predetermined bottom bits of both a TLB tag portion and a linear address to be compared are masked. If the target is the VRAM, the page frame size of paging is set to be larger than the page frame size when the access target is the system memory. Therefore, the TLB hit ratio can be improved when the access target is the VRAM, thus requiring less processing to update the TLB. This improves the drawing performance of the coprocessor.
Claims15
In an information processing system having a central processing unit (CPU), a system memory for storing data and instructions to be processed by the CPU, a video memory for storing an image data, display controller means for displaying the image data stored by the video memory on a display, means for communicating data between the CPU, the system memory and the display controller means, the display controller means comprises:
- means for generating a linear address;
- buffer means for storing at least two pairs of linear address tags having N bits length and real page addresses having M bits length, the N and M are integral numbers;
- means, coupled to the address generating means, for determining whether a logical value of start linear address of the video memory is a logical value of the linear address;
- means for selecting one of the linear address tags stored in the buffer means and determining whether a logical value of top P bits of the selected linear address tag is a logical value of top P bits of the linear address, in the case that the start linear address of the video memory is the linear address, the P is an integral number and less than the N;
- and
- means, coupled to the address generating means and the determining means, for generating a physical address having L bits length, from top (M-P) bits of a real page address and bottom (L-M+P) bits of linear address to access the video memory, in the case that top P bits of the selected linear address tag is top P bits of the linear address.
In an information processing system having a central processing unit (CPU), a system memory for storing data and instructions to be processed by the CPU, a video memory for storing an image data, display controller means for displaying the image data stored by the video memory on a display, means for communicating data between the CPU, the system memory and the display controller means, the display controller means comprises:
- means for generating a linear address;
- buffer means for storing at least two pairs of linear address tags having N bits length and real page addresses having M bits length, the N and M are integral numbers;
- means, coupled to the address generating means, for determining whether a logical value of start linear address of the video memory is a logical value of the linear address and
- means for passing a physical address as the linear address to access the video memory, in the case that the start linear address of the video memory is the linear address.
Apparatus for displaying the image data on a display, the apparatus comprising:
- a system memory for storing data and instructions;
- a system microprocessor for processing data in accordance with the instructions;
- a video memory for storing the image data;
- display controller means for displaying the image data stored by the video memory on a display;
- means for communicating data between the system microprocessor, the system memory and the display controller means;
- coprocessor means for addressing either a real or virtual memory, wherein the coprocessor means includes:
- means for generating a linear address;
- means for passing a physical address as the linear address to the system memory when a logical value of a start linear address of the video memory is a logical value of the generated linear address and passing the physical address as the translated address to the video memory after translating the linear address through a virtual address translation circuit when addressing virtual memory, the virtual address translation circuit having means for translating the linear address from the coprocessor means to a physical address of a page directory and page table;
- and
- buffer means for storing at least four pairs of linear address tags and real page addresses corresponding to source, pattern, mask and destination entry.
Dependencies are inferred from the claim text.