US 5,473,275 A · Switched-current bilinear integrator sampling input current on both phases of clock signal

Abstract

A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which, during a first phase of a clock cycle, an input current is fed to the inputs of the current memory cells and during a second phase of the clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2). A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell and an inverted, scaled version of the current stored in the first memoy cell.

Claims20

Dependent claims

A switched-current bilinear integrator comprising:

first and second interconnected current memory cells, means for feeding an input current to be integrated to respective inputs of the current memory cells during a first portion of a cycle of a clock signal, means for feeding a version of the input current of opposite polarity to the inputs of the current memory cells during a second portion of the cycle of the clock signal, means for producing a version of an output current of the second current memory cell of opposite polarity, means for combining an output current of the first current memory cell with the version of the output current of the second current memory cell of opposite polarity, and means for deriving an integrated input current from an output of the combining means.

A switched-current bilinear integrator comprising:

first and second interconnected current memory cells each having an input and an output,
an input terminal for supplying to the integrator an input current to be integrated,
switching means for selectively coupling said input terminal to the inputs of the first and second current memory cells so as to supply thereto the input current and an inverted form of said input current during respective first and second portions of a cycle of a clock signal, and means for combining an output current of the first current memory cell with an inverted form of an output current of the second current memory cell thereby to produce at an output of the combining means an output current which is an integrated version of the input current at said input terminal.

A differential switched current bilinear integrator comprising:

first and second input terminals for supplying to the integrator differential input currents,
first and second differential output current terminals of the integrator,
a first current memory circuit including first and second current memory cells each having an input and an output,
a second current memory circuit including third and fourth current memory cells each having an input and an output,
means for coupling said first and second output current terminals to respective outputs of the current memory cells, and
switching means coupling said first and second input terminals to respective inputs of the current memory cells so as to change over the connections between the input terminals and the inputs of the current memory cells in a manner so as to produce a current inversion function between first and second phases of a clock cycle of a clock signal that controls the operation of said switching means.

3 more elements

Dependencies are inferred from the claim text.

Switched-current bilinear integrator sampling input current on both phases of clock signal

Life of this patent

Switched-current bilinear integrator sampling input current on both phases of clock signal

Life of this patent

Abstract

Claims20