Microprocessor output driver
AssigneeDallas Semiconductor Corporation
InventorsWendell L. Little, Stephen N. Grider, Joseph W. Triece
Life of this patent
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Abstract
A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.
Claims58
An integrated circuit output driver, comprising:
- (a) an output transistor electrically coupling an output pad to a reference voltage;
- (b) a first bias circuit for said output transistor, said first bias circuit dynamically changes in response to changes of impedance of said output pad;
- (c) a second bias circuit for said output transistor differing from said first bias circuit;
- and
- (d) switching circuitry electrically coupled to said first and second bias circuits, said switching circuitry deactivating said first bias circuit and activating said second bias circuit.
An output driver, comprising:
- (a) an output transistor network electrically coupling an output pad to a reference voltage;
- (b) a first bias circuit for said output transistor network, said first bias circuit is self-regulating;
- (c) a second bias circuit for said output transistor network differing from said first bias circuit;
- and
- (d) switching circuitry electrically coupled to said first and second bias circuits, said switching circuitry selectably activating said first bias circuit and said second bias circuit.
An output driver, comprising:
- (a) an output transistor network electrically coupling an output pad to a reference voltage;
- (b) a first bias circuit for said output transistor network, said first bias circuit having a feedback relationship with said output pad to adjust bias of said first bias circuit;
- (c) a second bias circuit for said output transistor network differing from said first bias circuit;
- and
- (d) switching circuitry electrically coupled to said first and second bias circuits, said switching circuitry deactivating said first bias circuit and activating said second bias circuit.
Dependencies are inferred from the claim text.