Negative feedback to reduce voltage oscillation in CMOS output buffers
AssigneeAdvanced Micro Devices, Inc.
InventorQazi Mahmood
Life of this patent
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Abstract
A CMOS output buffer circuit includes negative feedback means for significantly reducing voltage oscillation. The buffer circuit is comprised of a pull-up transistor (P1), a pull-down transistor (N1), a first reference voltage generator circuit (44), a second reference voltage generator circuit (54), a first negative feedback circuit (48), and a second negative feedback circuit (58). First and second negative feedback circuits are coupled between the internal power supply potential/ground potential nodes and the gates of the pull-up/pull-down driver transistors so as to reduce the rate of change of the transient charging/discharging currents, respectively.
Claims17
A CMOS output buffer circuit for providing an output signal at an output node which has significantly reduced voltage oscillation, comprising:
- a pull-up transistor (P1) having one of its main electrodes connected to a power supply potential node and its other one of its main electrodes connected to the output node, said pull-up transistor having its gate electrode connected to receive a first control signal for generating a transition from a low logic level to a high logic level at the output node;
- a pull-down transistor (N1) having one of its main electrodes connected to the output node and the other one of its main electrodes connected to a ground potential node, said pull-down transistor having its gate electrode connected to receive a second control signal for generating a transition from the high logic level to the low logic level at the output node;
- first reference voltage generator means (44) including a first load transistor (N2) for generating a first clamp voltage to the gate of said pull-up transistor;
- second reference voltage generator means (54) including a second load transistor (P3) for generating a second clamp voltage to the gate of said pull-down transistor;
- first negative feedback means (48) responsive to voltage oscillation generated at the power supply potential node for generating a first negative feedback signal to the gate of said first load transistor to slow down the slew rate of the voltage at the gate of said pull-up transistor during the low-to-high transition, thereby reducing significantly the voltage oscillation at the power supply potential node;
- and
- second negative feedback means (58) responsive to voltage oscillation generated at the ground potential node for generating a second negative feedback signal to the gate of said second load transistor to slow down the slew rate of the voltage at the gate of said pull-down transistor during the high-to-low transition, thereby reducing significantly the voltage oscillation at the ground potential node.
A CMOS output buffer circuit for providing an output signal at an output node which has significantly reduced voltage oscillation, comprising:
- a pull-up transistor (P1) having one of its main electrodes connected to a power supply potential node and its other one of its main electrodes connected to the output node, said pull-up transistor having its gate electrode connected to receive a first control signal for generating a transition from a low logic level to a high logic level at the output node;
- a pull-down transistor (N1) having one of its main electrodes connected to the output node and the other one of its main electrodes connected to a ground potential node, said pull-down transistor having its gate electrode connected to receive a second control signal for generating a transition from the high logic level to the low logic level at the output node;
- reference voltage generator means (54) including a load transistor (P3) for generating a clamp voltage to the gate of said pull-down transistor;
- and
- negative feedback means (58) responsive to voltage oscillation generated at the ground potential node for generating a negative feedback signal to the gate of said load transistor to slow down the slew rate of the voltage at the gate of said pull-down transistor during the high-to-low transition, thereby reducing significantly the voltage oscillation at the ground potential node.
A CMOS output buffer circuit for providing an output signal at an output node which has significantly reduced voltage oscillation, comprising:
- pull-up transistor means (P1) for generating a transition from the low logic level to a high logic level at the output node;
- said pull-up transistor means including a P-channel MOS transistor;
- pull-down transistor means (P2) for generating a transition from the high logic level to the low logic level at the output node;
- said pull-down transistor means including an N-channel MOS transistor;
- first negative feedback means (48) for reducing the rate of change of the transient charging current in said pull-up transistor means during the low-to-high transition so as to reduce significantly the voltage oscillation at a power supply potential node;
- said first negative feedback means including a supply bounce sensing circuit (48) which is formed of a negative half-wave rectifier circuit (50) and a first voltage amplifier circuit (52), said negative rectifier circuit having its input connected to an internal-power supply node and an output, said voltage amplifier circuit having its input connected to the output of said negative rectifier circuit and its output connected to the gate of a first load transistor (N2);
- and
- second negative feedback means (58) for reducing the rate of change of the transient discharging current in said pull-down transistor means during the high-to-low transition so as to significantly reduce the voltage oscillation at a ground potential node.
Dependencies are inferred from the claim text.