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US 5,473,198 AGranted
Semiconductor memory device bonding pad arrangement
AssigneesHitachi, Ltd., Hitachi Device Engineering Co., Ltd.
InventorsKouki Hagiya, Ken Shibata
Life of this patent
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Abstract
A semiconductor memory device having inner lead portions of a plurality of leads disposed through at least one insulating film on a semiconductor chip and electrically insulated from the semiconductor chip, includes bonding pads for at least data input/output arranged in two rows axially symmetrically in a substantially central portion of the semiconductor chip interposed between memory arrays and bonding wires for connecting the inner lead portions and the bonding pads.
Claims17
A semiconductor memory device, comprising:
- a semiconductor chip having a main surface and memory array blocks formed on said main surface, and a plurality of bonding pads formed on said main surface at a substantially center portion of said main surface, said plurality of bonding pads including a first group of bonding pads extending in a first part of the substantially center portion, and a second group of bonding pads extending in a second part of the substantially center portion;
- a resin molding for sealing said semiconductor chip;
- and
- a plurality of leads, one end of each of said plurality of leads being positioned above said main surface of said semiconductor chip and electrically connected to a corresponding one of said plurality of bonding pads, and the other end of each of said plurality of leads being positioned outside of said resin molding, wherein
- said bonding pads of said first group are arranged in two rows, and said bonding pads of said second group are arranged in one row, and wherein
- said bonding pads of said first group include bonding pads for data input/output.
3 more elements
A semiconductor memory system comprising:
- a substrate;
- and
- two semiconductor memory devices mounted respectively on one side and an opposed side of said substrate, so that a principal surface of one of said two memory devices is opposed to an opposite surface of the other of said two memory devices through the substrate, each of the two memory devices comprising:
- a semiconductor chip having a main surface and memory array blocks formed on said main surface, and a plurality of bonding pads formed on said main surface at a substantially center portion of said main surface, said plurality of bonding pads including a first group of bonding pads extending in a first part of the substantially center portion, and a second group of bonding pads extending in a second part of the substantially center portion;
- a resin molding for sealing said semiconductor chip;
- and
- a plurality of leads, one end of each of said plurality of leads being positioned above said main surface of said semiconductor chip and electrically connected to a corresponding one of said plurality of bonding pads, and the other end of each of said plurality of leads being positioned outside of said resin molding, wherein
- said bonding pads of said first group are arranged in two rows, and said bonding pads of said second group are arranged in one row, and wherein
- said bonding pads of said first group include bonding pads for data input/output.
6 more elements
A semiconductor memory device system, comprising:
- a semiconductor array including a plurality of semiconductor memory devices;
- a central processing unit for controlling writing/reading of data of said semiconductor array;
- and
- an interface circuit for interfacing said central processing unit and said semiconductor array,
- wherein each of said plurality of semiconductor memory devices comprises:
- a semiconductor chip having a main surface and memory array blocks formed on said main surface, and a plurality of bonding pads formed on said main surface at a substantially center portion of said main surface, said plurality of bonding pads including a first group of bonding pads extending in a first part of the substantially center portion, and a second group of bonding pads extending in a second part of the substantially center portion;
- a resin molding for sealing said semiconductor chip;
- and
- a plurality of leads, one end of each of said plurality of leads being positioned above said main surface of said semiconductor chip and electrically connected to a corresponding one of said plurality of bonding pads, and the other end of each of said plurality of leads being positioned outside of said resin molding, wherein
- said bonding pads of said first group are arranged in two rows, and said bonding pads of said second group are arranged in one row, and wherein
- said bonding pads of said first group include bonding pads for data input/output.
8 more elements
Dependencies are inferred from the claim text.