Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices

Abstract

A new method of obtaining a consistent controllable tunnel oxide near the source/drain edge of a contactless memory cell is described. A thick gate oxide layer is grown on a semiconductor substrate. A first polysilicon layer is deposited overlying the thick gate oxide layer. A silicon nitride layer followed by a silicon oxide layer are deposited overlying the first polysilicon layer. The silicon oxide, silicon nitride, and first polysilicon layers are patterned and etched. Arsenic ions are implanted through the thick gate oxide layer into the substrate to form buried source and drain bit lines within the substrate. A second layer of silicon nitride is deposited over the patterned layers and anisotropically etched to form sidewall spacers. SATO (self-aligned thick oxide) oxidation is performed over the N+ area. The silicon nitride spacers are etched away whereby a portion of the thick gate oxide underlying the spacers is exposed. The silicon oxide layer is removed along with the exposed thick gate oxide. The thin tunnel oxide is regrown in the region where the silicon nitride spacers were removed. The silicon nitride layer is removed followed by deposition of a second layer of polysilicon overlying the first polysilicon layer. This layer is patterned such that it is overlying the SATO area to form the floating gate. An interpoly dielectric layer is deposited followed by a third polysilicon layer which is deposited and patterned to form the control gate completing formation of the memory cell.

Dependencies are inferred from the claim text.