Vertical insulated gate transistor and method of manufacture

A method of manufacturing a vertical insulated gate transistor, comprising the steps of:

• (1) continuously epitaxially growing a first semiconductor region of first conductivity type having a high-impurity-concentration, a second semiconductor region of second conductivity type, and a third semiconductor region having a low-Impurity-concentration on a substrate of first conductivity type having a high-impurity concentration serving as a source region, and forming a truncated U groove from the top surface of the third semiconductor region to reach the first semiconductor region;
• (2) disposing a wide band gap material having a wider band gap than the second semiconductor region on the bottom and sidewall of the truncated U groove, and
• burying high conductive material in the wide band gap material to form a buried gate electrode;
• and
• (3) forming a high-impurity-concentration fourth semiconductor region of first conductivity type serving as a drain region on the top surface of the third semiconductor region in a self-aligning manner employing said wide band gap material as a mask.

A method of manufacturing a vertical insulated gate transistor, comprising the steps of:

• (1) continuously epitaxially growing a high-impurity-concentration first semiconductor region of first conductivity type, a second semiconductor region of second conductivity type, and a low-impurity-concentration third semiconductor region on a high-impurity-concentration substrate of first conductivity type serving as a source region, forming a V-shaped groove on the top surface of the third semiconductor region, filling the V-shaped groove with wide band gap material having a wider band gap than the second semiconductor region, and forming a U groove at the center of the V-shaped groove downward to the first semiconductor region, to thereby form a truncated U groove;
• (2) forming an oxidization resistive film only on the sidewall of the U groove, selectively oxidizing the bottom of the U groove with use of the oxidization resistive film, to form a thick oxide film only on the bottom of the U groove, removing the oxidization resistive film, forming a gate oxide film on the sidewall of the U groove, and filling the U groove with highly conductive material serving as a gate electrode;
• and
• (3) employing said wide band gap material as a mask and forming a high-impurity-concentration fourth semiconductor region of first conductivity type serving as a drain region on the top surface of the third semiconductor region in a self-aligning manner.