US 5,472,887 AGranted

Method of fabricating semiconductor device having high-and low-voltage MOS transistors

AssigneeTexas Instruments Incorporated

InventorsLouis N. Hutter, Jeffrey P. Smith

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Abstract

A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-116d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

Claims8

Dependent claims

A method for forming a semiconductor device, comprising the steps of:

forming first and second gates over and insulated from a layer of P type semiconductor material;
forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of p type semiconductor material adjacent said first gate;
doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate;
removing said mask;
forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate;
forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions;
forming a fourth pair of N type regions self-aligned with said first pair of sidewall spacers and a fifth pair of N type regions self-aligned with said second pair of sidewall spacers, said fourth and fifth pairs of N type regions extending farther into said layer of P type semiconductor material than said second and third pairs of N type regions, said second and third pairs of N type regions being more heavily doped than said fourth and fifth pairs of N type regions.

4 more elements

A method for forming a semiconductor device, comprising the steps of:

forming first and second gates over and insulated from a layer of P type semiconductor material;
forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of P type semiconductor material adjacent said first gate;
doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate;
removing said mask;
forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate;
forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions;
forming an N well in said layer of P type semiconductor material;
forming a third gate and a fourth gate over and insulated from said N well;
forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate;
forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers and a second pair of sidewall spacer extension regions formed over said fourth pair of sidewall spacers;
forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.

8 more elements

A method for forming a semiconductor device, comprising the steps of:

forming first and second gates over and insulated from a layer of P type semiconductor material;
forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of P type semiconductor material adjacent said first gate;
doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate;
removing said mask;
forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate;
forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions;
forming an N well in said layer of P type semiconductor material;
forming a third gate and a fourth gate over and insulated from said N well;
forming a pair of N type regions in said N well self-aligned with said third gate;
forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate;
forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said pair of third sidewall spacers and a second pair of sidewall spacer extension regions formed over said pair of fourth sidewall spacers;
forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.

9 more elements

A method for forming a semiconductor device, comprising the steps of:

forming first and second gates over and insulated from a layer of P type semiconductor material;
forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of P type semiconductor material adjacent said first gate;
doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate;
removing said mask;
forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate;
forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions;
forming an N well in said layer of P type semiconductor material;
forming a third gate and a fourth gate over and insulated from said N well;
forming a pair of N type regions in said N well self-aligned with said third gate;
forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate;
forming a first pair of P type regions self-aligned with said third pair of sidewall spacers and a second pair of P type regions self-aligned with said fourth pair of sidewall spacers.

8 more elements

Dependencies are inferred from the claim text.