Method for implementing a high speed computer graphics bus

In a computer system having a system bus, a processing component coupled to said system bus, and a display component coupled to said system bus, a process for high speed transfer of information between said processing component and said display component, said process comprising the steps of:

• (a) receiving an instruction from a system memory, said instruction received by said processing component;
• (b) decoding said instruction in order to determine a destination address of said instruction, said instruction decoded by said processing component;
• (c) comparing said destination address of said instruction using registers defining a space range of said display component, said destination address compared by said processing component;
• (d) placing said instruction onto said system bus if said destination address does not correspond to said display component space range as programmed in said registers, said instruction placed onto said system bus by said processing component;
• (e) generating a start signal and placing said start signal onto a high speed bus if said destination address corresponds to said display component space range as programmed in said registers, said high speed bus coupling said processing component and said display component, said start signal generated by said processing component;
• (f) placing a command corresponding to said display component onto said high speed bus after said start signal has been placed on said high speed bus, said command placed onto said high speed bus by said processing component;
• (g) receiving said start signal from said processing component and selecting said high speed bus, said start signal received by said display component, and said high speed bus selected by said display component;
• (h) placing a busy signal onto said high speed bus indicating that a high speed bus cycle is in progress, said busy signal placed onto said high speed bus by said processing component;
• (i) receiving said command and instruction from said processing component by said display component;
• (j) processing said instruction by said display component;
• (k) placing a ready signal onto said high speed bus indicating that said display component is finished with said command and said instruction, said ready signal placed onto said high speed bus by said display component;
• and
• (l) after receiving said ready signal sent by said display component, completing said high speed bus cycle by deactivating said busy signal, said busy signal deactivated by said processing component.