Apparatus for arbitrating for a high speed direct memory access bus

An apparatus for use in an electronic data processing system having a DMA controller, a DMA data bus, and a microprocessor that is connected to a processor address bus, a processor data bus and a processor control bus, comprising:

• input/output means for receiving a data word from an external high speed bus, said input/output means having a buffer register to store the data word for subsequent transfer to the DMA data bus;
• first multiplexer means for multiplexing control signals to the input/output means;
• DMA RAM means connected to the DMA data bus for receiving and storing the data word;
• second multiplexer means for multiplexing the control signals and address signals to the DMA RAM means;
• gateway means for switchably connecting or disconnecting the processor data bus to said DMA data bus, said gateway means is responsive to a control signal from the DMA controller for either connecting or disconnecting the processor data bus from the DMA data bus;
• said first multiplexer means has a first input connected to the processor control bus for receiving control signals from said microprocessor and a second input connected to a DMA control bus for receiving control signals from said DMA controller;
• said second multiplexer means has a first input connected to the processor control bus, a second input connected to the processor address bus, a third input connected to the DMA control bus and a fourth input connected to a DMA address bus;
• and
• an arbitration circuit is included as a part of the DMA controller, the arbitration circuit having an arbitration control input connected to and controlled by said microprocessor, a select output connected to said first and second multiplexers, and a gateway control output connected to said gateway means;
• if the microprocessor outputs a first arbitration signal to said arbitration circuit said arbitration circuit multiplexes said second input of said first multiplexer means and said third and fourth inputs of said second multiplexer means from the DMA controller to said input/output means for receiving a data word from an external high speed bus and said high speed RAM means respectively;
• if the microprocessor outputs a second arbitration signal to said arbitration circuit said arbitration circuit multiplexes said first input of said first multiplexer means and said first and second inputs of said second multiplexer means from the microprocessor to said input/output means and said DMA RAM means respectively, and switches said gateway means to connect said DMA data bus to said processor data bus.