US 5,471,638 AGranted

Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests

AssigneeBull HN Inforamtion Systems Inc.

InventorJames W. Keeley

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Abstract

A processor couples to a system bus and includes a high performance microprocessor which tightly couples to a local memory. The processor is organized at the interface level into a plurality of interface sections which include a corresponding number of state machines for enabling the simultaneous processing of a plurality of different types of transactions or requests under all conditions. One interface section is organized to include the system visible registers which are accessible for reading and writing by I/O commands received from the system bus. Another section processes memory commands received from the system bus while a further section processes read/write and I/O commands issued to the system bus by the processor.

Claims13

Dependent claims

A processing unit for processing a plurality of different types of system bus transactions, said processing unit being tightly coupled to a system bus which is operated according to a predetermined protocol, said processing unit including a microprocessor, a local memory tightly coupled to said microprocessor, a plurality of system visible registers and a system bus interface operatively coupled to said microprocessor, said local memory and said system visible registers for receiving and transmitting different types of requests including read/write commands, input/output commands and external read memory commands, said system bus interface comprising:

a first interface section coupled to said system bus and to said microprocessor for processing a first type of request corresponding to said read/write commands generated and transferred by said microprocessor to said system bus;
a second interface section coupled to said local memory for processing a second type of request corresponding to said external read memory commands transferred to said local memory from said system bus;
and,
a third interface section coupled to said system bus in common to said plurality of system visible registers for processing a third type of request corresponding to said external input/output commands received from said system bus reading and writing different ones of said registers, said interface sections each including a state machine programmed for independently processing each command until receipt of either a signal from said system bus indicating a successful completion of said each command or until completion of a predetermined retry procedure specific to the type of command being executed as defined by said predetermined protocol of said system bus thereby enabling simultaneous independent processing of said plurality of different types of bus transactions by said processing unit.

1 more element

A processing unit which tightly couples to a system bus which is operated according to a predetermined protocol, said processing unit including a microprocessor, a local memory tightly coupled to said microprocessor, a plurality of system visible registers and a system bus interface operatively coupled to said microprocessor, said local memory and to said plurality of system visible registers for receiving and transmitting to said system bus, different types of requests including processor read/write commands, external memory read commands and external input/output commands, said system bus interface comprising:

a first interface section coupled to said microprocessor for processing said read/write commands generated by said microprocessor and transferred to said system bus which require execution of a first type of processing sequence for completion;
a second interface section coupled to said local memory for processing said external read memory commands received from said system bus and transferred to said local memory which require execution of a second type of processing sequence for completion;
a third interface section coupled to in common to said plurality of system visible registers for processing said external input/output commands received from said system bus for reading different ones of said registers which require execution of a third type of processing sequence for completion;
and,
each of said first, said second and said third interface sections including a state machine programmed for independently processing each command according to said first, second and third type of processing sequence, respectively, until receipt of a signal from said system bus indicating either a successful completion of said each command or until completion of a predetermined retry procedure specific to a type of command being executed as defined by said predetermined protocol of said system bus for enabling simultaneously independent processing of said different types of requests by said processing unit.

2 more elements

Dependencies are inferred from the claim text.