Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer

In a computer system comprising a processor module including a processor and having a first operating clock, a memory subsystem including a number of pre-installed memory modules and having a second operating clock independent of the first operating clock, a bus coupling the processor module and the memory subsystem to each other, a method for sequentially conducting a plurality of bus transactions between the processor and the memory modules, the method comprising the steps of:

• a) initiating and facilitating each bus transaction by the processor module by generating and maintaining a first plurality of request signals on the bus for each bus transaction, one transaction at a time, referencing the first operating clock;
• b) conditionally outputting first response signals onto the bus for a bus transaction by the first pre-installed memory module, responsive to the bus transaction's request signals, referencing the second operating clock, whenever the bus transaction's request signals address the first pre-installed memory module, the first response signals conveying access characteristic information about a first pre-installed memory module of the memory subsystem;
• c) conditionally determining a time value in terms of the first operating clock for a bus transaction by the processor, referencing the first operating clock, whenever the request signals solicited the first response signals conveying access characteristic information, the first operating clock based time value being determined dynamically using the responsive access characteristic information and denoting an amount of time in terms of the first operating clock the processor is to wait before concluding the first bus transaction;
• (d) conditionally bursting a series of response data onto the bus for a bus transaction by the first pre-installed memory module, responsive to the bus transaction's request signals, referencing the independent second operating clock, whenever the bus transaction's request signals denote a memory burst read bus transaction, and the bus transactions' request signals address the first pre-installed memory module;
• (e) conditionally latching a series of response data off the bus for a bus transaction by the processor, referencing the first operating clock, whenever the bus transaction's request signals denote a memory burst read bus transaction, a first operating clock based time value has been dynamically determined for the bus transaction, and time has elapsed by the first operating clock based time value determined since the bus transaction was initiated;
• and
• f) concluding by the processor each bus transaction whose request signals solicited the first response signals, by ceasing to maintain the request signals of the bus transaction on the bus, after having so waited accordingly, and allowing time in terms of the first operating clock by the processor for the last of the response data of the bus transaction to be latched.