Idiom recognizer within a register alias table

In a mechanism for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being associated with a current set of operations, an apparatus for selectively overriding partial width stalls of said renaming mechanism, said apparatus comprising:

• low bank array means for renaming said logical registers that are either low byte logical registers or logical registers that are larger than byte size, said low bank array means also for providing a low bank physical register size and a low bank zero bit for each of said physical registers, wherein said logical registers have logical register sizes and said low bank zero bits for indicating whether a most significant portion of said logical registers contains zeros;
• high bank array means, coupled to said low bank array means, for renaming said logical registers that are high byte logical registers to said physical registers, said high bank array means also for providing a high bank physical register size and a high bank zero bit for each of said physical registers, wherein said high bank zero bits for indicating whether a high byte of said logical registers contain zeros;
• size comparison means, coupled to said high bank array means and said low bank array means, for comparing said logical register sizes to said high bank physical register sizes and said low bank physical register sizes;
• partial width stall means, coupled to said size comparison means, said high bank array means, and said low bank array means, for stalling renaming of a first logical register by said low bank array means when a first logical register size is larger than either a first high bank physical register size or a first low bank physical register size, wherein the smaller of said first high bank physical register size and said first low bank physical register size corresponds to a first partial width register to which said first logical register would otherwise be renamed, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• partial width stall override means, coupled to said partial width stall means, for overriding said stalling of said array means when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

In a mechanism for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being associated with a current set of operations, an apparatus for selectively overriding partial width stalls of said renaming mechanism, said apparatus comprising:

• an array for renaming said current set of logical registers to said current set of physical registers by storing rename values corresponding to said physical registers in array locations associated with said logical registers, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, wherein each of said physical registers has a corresponding set of zero bits for indicating whether predetermined portions of said logical registers contain zeros;
• a size comparator, coupled to said array, for comparing said logical register sizes to said physical register sizes;
• a partial width stall detector, coupled to said size comparator and said array, for stalling renaming of a first logical register by said array when said first logical register is of larger size than a corresponding first partial width register to which said first logical register would otherwise be renamed by said array, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• a partial width stall overrider, coupled to said partial width stall detector, for overriding said stalling of said array when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion contains of said first logical register zeros.

In a mechanism for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being associated with a current set of operations, an apparatus for selectively overriding partial width stalls of said renaming mechanism, said apparatus comprising:

• a low bank array for renaming said logical registers that are either low byte logical registers or logical registers that are larger than byte size, said low bank array renaming by storing rename values corresponding to said physical registers in low bank array locations associated with said logical registers, said low bank array also for providing a low bank physical register size and a low bank zero bit for each of said physical registers, wherein said logical registers have logical register sizes and said low bank zero bits for indicating whether a most significant portion of said logical registers contains zeros;
• a high bank array, coupled to said low bank array, for renaming said logical registers that are high byte logical registers to said physical registers, said high bank array renaming by storing rename values corresponding to said physical registers in high bank array locations associated with said high byte logical registers, said high bank array also for providing a high bank physical register size and a high bank zero bit for each of said physical registers, wherein said high bank zero bits for indicating whether a high byte of said logical registers contain zeros;
• a size comparator, coupled to said high bank array and said low bank array, for comparing said logical register sizes to said high bank physical register sizes and said low bank physical register sizes;
• a partial width stall detector, coupled to said size comparator, said high bank array, and said low bank array, for stalling renaming of a first logical register by said low bank array when a first logical register size is larger than either a first high bank physical register size or a first low bank physical register size, wherein the smaller of said first high bank physical register size and said first low bank physical register size corresponds to a first partial width register to which said first logical register would otherwise be renamed, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• a partial width stall overrider, coupled to said partial width stall detector, for overriding said stalling of said array means when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

A microprocessor comprising:

• a bus interface unit for interfacing with a bus;
• an instruction decode and fetch unit coupled to said bus interface unit for decoding a current set of operations for a given cycle;
• a plurality of execution units coupled to said instruction decode and fetch means for simultaneously executing the decoded operations;
• and
• means for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being specified by a current set of operations, said renaming means including,
• array means for renaming said current set of logical registers to said current set of physical registers, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, wherein each of said physical registers has a corresponding set of zero bits for indicating whether predetermined portions of said logical registers contain zeros;
• size comparison means, coupled to said array means, for comparing said logical register sizes to said physical register sizes;
• partial width stall means, coupled to said size comparison means and said array means, for stalling renaming of a first logical register by said array means when said first logical register is of larger size than a corresponding first partial width register to which said first logical register would otherwise be renamed by said array means, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• partial width stall override means, coupled to said partial width stall means, for overriding said stalling of said array means when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

A microprocessor comprising:

• a bus interface unit for interfacing with a bus;
• an instruction decode and fetch unit coupled to said bus interface unit for decoding a current set of operations for a given cycle;
• a plurality of execution units coupled to the instruction decode and fetch unit for simultaneously executing the decoded operations;
• and
• a renaming circuit coupled to said instruction decode and fetch unit, said renaming circuit for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being specified by a current set of operations, said renaming circuit including,
• an array for renaming said current set of logical registers to said current set of physical registers by storing rename values corresponding to said physical registers in array locations associated with said logical registers, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, wherein each of said physical registers has a corresponding set of zero bits for indicating whether predetermined portions of said logical registers contain zeros;
• a size comparator, coupled to said array, for comparing said logical register sizes to said physical register sizes;
• a partial width stall detector, coupled to said size comparator and said array, for stalling renaming of a first logical register by said array when said first logical register is of larger size than a corresponding first partial width register to which said first logical register would otherwise be renamed by said array, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• a partial width stall overrider, coupled to said partial width stall detector, for overriding said stalling of said array when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

A computer system comprising:

• bus means for providing a communication interface;
• memory means coupled to said bus means for storing instructions and computer data;
• interface means coupled to said bus means for providing data input and data output to interface with a user;
• and
• microprocessor means coupled to said bus means for executing said instructions and processing said computer data, said microprocessor means having a means for renaming a current set of logical registers to a current set of physical registers, said current set of logical registers being associated with a current set of operations, said renaming means including,
• array means for renaming said current set of logical registers to said current set of physical registers, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, wherein each of said physical registers has a corresponding set of zero bits for indicating whether predetermined portions of said logical registers contain zeros;
• size comparison means, coupled to said array means, for comparing said logical register sizes to said physical register sizes;
• partial width stall means, coupled to said size comparison means and said array means, for stalling renaming of a first logical register by said array means when said first logical register is of larger size than a corresponding first partial width register to which said first logical register would otherwise be renamed by said array means, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• partial width stall override means, coupled to said partial width stall means, for overriding said stalling of said array means when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

A computer system comprising:

• a bus for providing communication interface;
• a memory coupled to said bus for storing instructions and computer data;
• an interface circuit coupled to said bus for providing data input and data output to interface with a user;
• and
• a microprocessor coupled to said bus means for executing said instructions and processing said computer data, said microprocessor having a renaming mechanism for renaming a current set of logical registers to a current set of physical registers, said current set of logical registers being associated with a current set of operations, said renaming mechanism including,
• an array for renaming said current set of logical registers to said current set of physical registers by storing rename values corresponding to said physical registers in array locations associated with said logical registers, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, wherein each of said physical registers has a corresponding set of zero bits for indicating whether predetermined portions of said logical registers contain zeros;
• a size comparator, coupled to said array, for comparing said logical register sizes to said physical register sizes;
• a partial width stall detector, coupled to said size comparator and said array, for stalling renaming of a first logical register by said array when said first logical register is of larger size than a corresponding first partial width register to which said first logical register would otherwise be renamed by said array, said first logical register being one of said current set of logical registers, said first partial width register being part of a first physical register, said first physical register being one of said current set of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• and
• a partial width stall overrider, coupled to said partial width stall detector, for overriding said stalling of said array when a first set of zero bits corresponding to said first logical register indicates that said second contiguous portion of said first logical register contains zeros.

In a mechanism utilizing an array memory for renaming a current set of logical registers to a current set of physical registers of an extended register set, said current set of logical registers being associated with a current set of operations, wherein said logical registers and said physical registers have partial width registers, wherein said logical registers have logical register sizes and said physical registers have physical register sizes, a method for detecting and selectively overriding partial width stall conditions, said method comprising the steps of:

• temporarily assigning said current set of logical registers to said current set of physical registers;
• comparing said logical register sizes to said physical register sizes;
• detecting a partial width stall condition when a first logical register is of larger size than a first partial width register to which said first logical register is temporarily assigned, said first partial width register being part of a first physical register of said current said of physical registers, wherein said first logical register has a first and second contiguous portions, said first partial width register corresponds to said first contiguous portion, said first physical register has a third portion contiguous with said first partial width register, and said third portion corresponds to said second portion;
• overriding said partial width stall condition when said second contiguous portion of said first logical register contains zeros;
• and
• renaming said current set of logical registers to said current set of physical registers when a partial width stall condition is detected but overridden.