System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred

A data transfer device for coupling a processor to a system bus, said data transfer device comprising:

• a processor bus system adapted for coupling to the processor for transfer of bus address information and bus data length information from the processor and for transfer of data to and from the processor;
• a plurality of addressable registers, each one of the addressable registers being coupled to the processor bus system, the plurality of addressable registers including:
• i) an address register for storing the bus address information and having a bus address output adapted for coupling to the system bus,
• ii) a bus data length register for storing the bus data length information and having a bus data length output, and
• iii) a data register for storing data and having a data output;
• a register address bus adapted for coupling to the processor for input of register address information;
• a decoder coupled to the register address bus and to each of the addressable registers for enabling one of the registers at a time for input of bus address information, bus data length information or data from the processor bus system as a function of the register address information placed on the register address bus by the processor, in a sequence of processor operating cycles;
• a bus data input adapted for coupling to the system bus for input of data from the system bus;
• an internal buffer memory system selectively coupled to each of the bus data input and the data output of the data register for input of write data to the internal buffer memory system;
• the internal buffer memory system having a bus data output adapted for coupling to the system bus and a processor data output coupled to the processor bus system;
• a control state machine system coupled to each of the internal buffer memory system, the bus data length register output and the decoder and including an internal memory address generator for generating memory addresses for controllably writing data to the internal buffer memory system via the selective coupling to the data output of the data register and the bus data input;
• the control state machine system being responsive to the enabling of the bus data length register by the decoder to independently initiate a bus transaction with the system bus to write data from the system bus to the internal buffer memory system via the bus data input as a function of the bus address information output of the address register and the bus data length information output by the bus data length register.