Dynamically programmable timer-counter having enable mode for timer data load and monitoring circuit to allow enable mode only upon time-out

A programmable timer circuit comprising:

• programmable timer counter means having timer counter input means for receiving count data and for receiving a periodical clock signal and counting to a count representing said count data in response to said clock signal and having an output signal means for generating a signal representative of said count,
• a programmable means for generating count data in response to programming of said programmable means,
• timer data register means for receiving said count from said programmable means,
• first gate means having an enabled mode and an non-enabled mode for enabling loading of said timer data from said timer data register to said timer counter input mean only in said enabled mode,
• monitoring means for monitoring signal of said timer counter means and enabling said first gate means to said enabled mode selection only when said timer counter means has generated a time-out
• a timer output register in bus communication with said output of said timer counter means for writing each count of said timer count means in said timer output register, said timer output register to be responsive to a control signal from said programmable means for permitting said programmable means to read said timer count from said output register without run count of said timer.

A programmable timer circuit comprising:

• programmable timer counter means, wherein said timer circuit is a module of an application specific integrated circuit in bus communication with a programmable microprocessor and a plurality of memory devices for controlling the operation of a postage metering system, said timer means having input means for receiving a count data represent a count and for receiving a periodical clock signal and counting to said count in response to said clock signal for generating a signal representative of said count,
• programmable timer counter means having input means for receiving a count data and for receiving a periodical clock signal and counting to a count representing said count data in response to said clock signal and for an output means generating a signal representative of said count,
• a programmable means for generating count data in response to programming,
• timer data register means for receiving said count from said programmable means,
• first gate means having an enabled mode and an non-enabled mode for enabling loading of said count data from said timer data register means to said timer counter input mean only when said first gate means is in said enabled mode,
• monitoring means for monitoring said signal of said timer counter means and enabling said first gate means to said enabled mode only when said timer counter means has generated a time-out signal;
• a second gate means having an enabled mode in response to a control signal from said programmable means for permitting said programmable means to read data written to said timer data register means without disruption of the running count of said timer counter means,
• a timer output register in bus communication with said output of said timer counter means for writing each count of said timer count means in said timer output register, said timer output register to be responsive to a control signal from said microprocessor for permitting said microprocessor to read said count from said output register.