Multi-phase multi-access pipeline memory system
AssigneeAnalog Devices, Inc.
InventorDouglas Garde
Life of this patent
Estimating the term…
Abstract
A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
Claims12
A dual phase, dual access pipeline memory system comprising:
- first and second processors;
- a pipeline memory including latch means;
- bus means for connecting each of said processors with said pipeline memory;
- a clock circuit responsive to a clock signal, said clock circuit providing a first clock signal in phase with said system clock signal for operating said first processor, a second clock signal out of phase with said system clock signal for operating said second processor out of phase with said first processor and a third clock signal at twice the system clock signal rate, said third clock signal clocking said pipeline memory through said latch means to allow an address to be supplied to said pipeline memory by said first processor during one phase while said first processor is accessing data from the previous cycle in the same phase and, conversely, to allow an address to be supplied to said pipeline memory by said second processor during the other phase while the said second processor is accessing data from the previous cycle in the same phase.
A multi-phase, multi-access pipeline memory system, comprising:
- a quantity, n, of processors;
- a pipeline memory including latch means;
- bus means for interconnecting said processors and pipeline memory;
- a clock circuit, responsive to a system clock signal including means for dividing said system clock signal into n phases and for providing multiple clock signals corresponding to the n phases of said system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling said memory and each processor to operate at the system clock rate while allowing n accesses to said memory during each system clock signal period, one access for each processor.
Dependencies are inferred from the claim text.