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US 5,471,602 AGranted
System and method of scoreboarding individual cache line segments
AssigneeHewlett-Packard Company
InventorEric R. DeLano
Life of this patent
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AssigneeHewlett-Packard Company
InventorEric R. DeLano
Estimating the term…
A system and method for scoreboarding individual cache line units in order to reduce the cache store-miss penalty is disclosed. Store operations to cache addresses which generate a store-miss are allowed to occur during the same time period that a missing line is being retrieved from memory. The cache memory is divided into a plurality of cache lines, each of the cache lines having a plurality of data units. A store-scoreboard, associated with a selected one of the cache lines, maintains a record of the contents of the plurality of data units within the selected cache line. Memory access performance is improved by allowing stores which miss the cache to complete in advance of the miss copy-in and by allowing multiple stores to the same cache line (being retrieved from memory) to occur without a penalty during the latency period of the store miss. Furthermore, a "safety net" is provided for hinted store instructions. The store-scoreboard provides the infrastructure necessary to allow the computer system to verify whether the instruction stream which contains the hinted store has completed its intended obligation.
A system for updating a data cache memory during a store-miss for a designated store address, comprising:
A method of operating on a computer system having a central processing unit (CPU) and a cache memory for updating the contents of the cache memory, comprising the steps of:
In a computer-based system having a central processing unit (CPU) and a cache memory, wherein the cache memory has a plurality of cache lines, each cache line having a plurality of data units, an apparatus for updating the contents of the cache memory, comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Overlapped cache accessing, e.g. pipeline: with reload from main memory
Computing and data processing
Term ended 28 Nov 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates generally to the design of a cache memory and, more particularly, to a system and method of scoreboarding individual cache line segments in order to reduce the penalty associated with a cache store-miss.
2. Discussion of Related Art
The above and further advantages of this invention may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a block diagram of the general environment of the present invention;
FIG. 2 illustrates an example of scoreboarding an individual cache line segment in accordance with the present invention;
An example of an overall system in which the present invention could be used is generally described in Delano et al., "A High Speed Superscalar PA-RISC Processor", IEEE COMPCOM Spring '92 Digest of Papers, February 1992, which is incorporated herein by reference. The environment described in this article is selected for illustration purposes only. It is an example of one of many computer systems in which the present invention could be used.
Referring to FIG. 1, a processor chip 110 connects directly to an external 64-bit wide instruction cache 120 and an external 64-bit wide data cache 130. These caches are direct mapped and are composed of industry standard high speed SRAMs which are cycled at the processor frequency. At 100 MHz, each cache has a read bandwidth of 800 MB/sec and a write bandwidth of 400 MB/sec. The processor chip supports a D-Cache size from 4K up to 2 Mbytes and a I-Cache size from 4K up to 1 Mbyte. Note that the present invention can be implemented in any computer-based system that utilizes a memory hierarchy. Also note that the present invention is not limited to computer-based systems that only use a single level cache memory. The present invention works equally well with multi-level cache structures.
The cache addresses are hashed in order to reduce the cache miss rate. The present invention is applicable to either off-chip caches or on-chip caches. Note that although the preferred embodiment uses a hashing algorithm, the present invention is completely independent of the specific addressing algorithm employed.