US 5,471,598 AGranted

Data dependency detection and handling in a microprocessor with write buffer

AssigneeCyrix Corporation

InventorsMarc A. Quattromani, Raul A. Garibay, Jr., Nital Patwa, Mark W. Hervin

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Abstract

A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Claims6

Dependent claims

A microprocessor, comprising:

(a) a pipelined core unit including an address calculation stage, followed by an execution stage, followed by a writeback stage;
(b) a write buffer having a plurality of entries coupled to said execution stage and said writeback stage, each of said plurality of entries containing contents corresponding to a write instruction executed in said execution stage and written from said writeback stage, said contents including a data field, an address field, a data a valid control bit, and a non-cacheable write bit representing whether said write instruction is non-cacheable;
(c) a cache memory having a plurality of entries coupled to receive said data and address fields from said write buffer;
and,
(d) control logic circuitry coupled to said address calculation stage and to said write buffer, to compare an address of a read instruction in said address calculation stage to each of said plurality of address fields in said write buffer, and responsive to an address match, said data valid control bit being set, and said non-cacheable write bit being clear, bypassing said data field in said write buffer to said execution stage in said pipelined core unit.

2 more elements

Dependencies are inferred from the claim text.