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US 5,471,583 AGranted
FIFO buffer having write counter for generating empty flag value to be compared with read pointer value to indicate the buffer is full
AssigneeIntegrated Device Technology, Inc.
InventorsFu L. Au, Einat Yogev
Life of this patent
Estimating the term…
Abstract
To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated by generating an internal full or empty signal before the FIFO actually becomes full or empty.
Claims4
A FIFO buffer for sequentially transmitting data from a first digital system to a second digital system comprising:
- a memory circuit having a plurality of storage locations and having an input port and an output port;
- a write pointer logic circuit coupled to said memory circuit, said write pointer logic circuit having a first write counter, and a second write counter, wherein said first write counter generates a write pointer value indicating the storage location of said memory circuit to which incoming data is written, and wherein said second write counter generates an empty flag reference value, said empty flag reference value being greater than or equal to said write pointer value;
- a read pointer logic circuit coupled to said memory circuit , said read pointer logic circuit having a read counter, wherein said read counter generates a read pointer value indicating the storage location of said memory circuit from which outgoing data is read;
- and
- a flag logic circuit coupled to said write pointer logic circuit and to said read pointer logic circuit, wherein said flag logic circuit includes a comparator circuit for generating a comparator signal indicative of a predetermined relationship between said empty flag reference value and the read pointer value, wherein the comparator signal is associated with a first logical state when the FIFO buffer is filled with data and wherein the comparator signal makes a transition to a second logical state before the FIFO buffer becomes empty, and wherein said flag logic circuit further includes an empty flag output circuit coupled to an output line of said comparator circuit, said empty flag output circuit for selectively asserting an empty flag signal in response to a read signal when the comparator signal is in the second logical state.
2 more elements
A FIFO buffer for sequentially transmitting data from a first digital system to a second digital system comprising:
- a memory circuit having a plurality of storage locations and having an input port and an output port;
- a write pointer logic circuit coupled to said memory circuit, said write pointer logic circuit having a first write counter and a second write counter, wherein said first write counter generates a write pointer value indicating the storage location of said memory circuit to which incoming data is written, and wherein said second write counter generates a write full flag reference value, said write full flag reference value being greater than said write pointer value;
- a read pointer logic circuit coupled to said memory circuit, said read pointer logic circuit having a first read counter, and a second read counter wherein said first read counter generates a read pointer value indicating the storage location of said memory circuit from which outgoing data is read and wherein said second read counter generates a read full flag reference value, said read full flag value being less than or equal to said read pointer value;
- and
- a flag logic circuit coupled to said write pointer logic circuit and to said read pointer logic circuit, wherein said flag logic circuit includes a comparator circuit for generating a comparator signal indicative of a predetermined relationship between said write full flag reference value and said read full flag reference value, wherein the comparator signal is associated with a first logical state when the FIFO buffer is empty and wherein the comparator signal makes a transition to a second logical state before the FIFO buffer becomes full, and wherein said flag logic circuit further includes a full flag output circuit coupled to an output line of said comparator circuit, said full flag output circuit for selectively asserting a full flag signal in response to a write signal when the comparator signal is in the second logical state.
2 more elements
Dependencies are inferred from the claim text.