Hardware XOR sprite for computer display systems

Apparatus for controlling the color of pixels of a sprite overlaid on a portion of an image displayed on a video display unit (VDU) of a computer display system such that said sprite is visibly distinct from said displayed image, said computer display system including a graphics controller for activating a sprite control signal when a raster scanning beam of said VDU is at a pixel position on said VDU corresponding to said image portion upon which said sprite is overlaid and a video random access memory (VRAM) for storing said image in digital form such that each pixel of said image is stored as a word of image pixel data comprising at least one color component, and for outputting an image pixel data word of an image pixel to be displayed at said raster scanning beam pixel position, the apparatus comprising:

• a sprite random access memory (RAM) for storing a plurality of sprite data bits, wherein each of said sprite data bits corresponds to one of said sprite pixels and indicates whether said corresponding one of said sprite pixels is active;
• at least one logic gate having a first input electrically connected to said VRAM for receiving a most significant bit (MSB) of said at least one color component of said output image pixel data word and a second input electrically connected to an output of said sprite RAM;
• at least one logic circuit having a first input electrically connected to said VRAM for receiving said at least one color component MSB of said output image pixel data word, a second input electrically connected to an output of said at least one logic gate, and a third input electrically connected to said graphics controller for receiving said sprite control signal therefrom;
• wherein responsive to said sprite control logic signal being active, said sprite RAM outputs one of said sprite data bits corresponding to said raster scanning beam pixel position to said second input of said at least one logic gate;
• wherein responsive to said output one of said sprite data bits comprising a 0, said at least one logic gate outputs said at least one color component MSB of said output image pixel data word;
• wherein responsive to said output one of said sprite data bits comprising a 1, said at least one logic gate inverts said at least one color component MSB of said output image pixel data word and outputs said inverted at least one color component MSB of said output image pixel data word;
• wherein responsive to said sprite control signal being inactive, said at least one logic circuit outputs a signal applied to said first input thereof;
• and
• wherein further responsive to said sprite control signal being active, said at least one logic circuit outputs a signal applied to said second input thereof.

Apparatus for controlling a color of a sprite overlaid on an image displayed on a video display unit (VDU) of a computer display system such that said sprite is always visibly distinct from said displayed image, said computer display system including a graphics controller for selectively activating a sprite control signal for initiating display of said sprite and a video random access memory (VRAM) for storing said image in digital form in which each pixel of said image is represented by a word of pixel data comprising first, second and third color components, and for sequentially outputting pixel data words, the apparatus comprising:

• a sprite random access memory (RAM) for storing a plurality of sprite data bits, wherein each of said sprite data bits corresponds to a pixel of said sprite and indicates whether said corresponding sprite pixel is active;
• a first logic gate having a first input electrically connected to said VRAM for receiving said first color component MSB of a pixel data word output from said VRAM and a second input electrically connected to an output of said sprite RAM;
• a second logic gate having a first input electrically connected to said VRAM for receiving said second color component MSB of said output pixel data word and a second input electrically connected to said sprite RAM output;
• a third logic gate having a first input electrically connected to said VRAM for receiving said third color component MSB of said output pixel data word and a second input electrically connected to said sprite RAM output;
• a first logic circuit having a first input electrically connected to said VRAM for receiving said first color component MSB of said output pixel data word, a second input electrically connected to an output of said first logic gate, and a third input electrically connected to said graphics controller for receiving said sprite control signal therefrom;
• a second logic circuit having a first input electrically connected to said VRAM for receiving said second color component MSB of said output pixel data word, a second input electrically connected to an output of said second logic gate and a third input electrically connected to said graphics controller for receiving said sprite control signal therefrom and;
• a third logic circuit having a first input electrically connected to said VRAM for receiving said third color component MSB of said output pixel data word, a second input electrically connected to an output of said third logic gate and a third input electrically connected to said graphics controller for receiving said sprite control signal therefrom;
• wherein responsive to said sprite control logic signal being active, said sprite RAM outputs one of said sprite data bits said second input of each of said first, second and third logic gates;
• wherein responsive to said output one of said sprite data bits indicating that said corresponding sprite pixel is inactive, said first, second and third logic gates output said first, second and third color component MSBs of said output pixel data word, respectively;
• wherein responsive to said output one of said sprite data bits indicating that said corresponding sprite pixel is active, said first, second and third logic gates invert said first, second and third color component MSBs of said output pixel data word, respectively, and output said inverted first, second and third color component MSBs of said output pixel data word, respectively;
• wherein responsive to said sprite control signal being inactive, said first, second and third logic circuits respectively output signals applied to said first inputs thereof;
• and
• wherein further responsive to said sprite control signal being active, said first, second and third logic circuits respectively output signals applied to said second inputs thereof.