Active pixel sensor with intra-pixel charge transfer

An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

• a photogate overlying said substrate for accumulating photo-generated charge in an underlying portion of said substrate;
• a readout circuit comprising at least an output transistor formed in said substrate;
• a charge coupled device section formed on said substrate adjacent said photogate having a sensing node connected to said output transistor and at least one charge coupled device stage for transferring charge from said underlying portion of said substrate to said sensing node;
• wherein said sensing node of said charge coupled device stage comprises a floating node and said charge coupled device stage comprises a transfer gate between said floating node and said photogate;
• a drain diffusion connected to a drain bias voltage;
• a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal;
• wherein said readout circuit further comprises a double correlated sampling circuit comprising:
• a pair of sample and hold field effect transistors formed in said substrate, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said output transistor;
• a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors;
• means for sensing a potential of each of said sample and hold capacitors at respective intervals;
• and
• means for shorting across each of said pair of sample and hold capacitors simultaneously while said means for sensing measures a fixed pattern noise difference.

An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

• a photogate overlying said substrate for accumulating photo-generated charge in an underlying portion of said substrate;
• a readout circuit comprising at least an output transistor formed in said substrate;
• a charge coupled device section formed on said substrate adjacent said photogate having a sensing node connected to said output transistor and at least one charge coupled device stage for transferring charge from said underlying portion of said substrate to said sensing node;
• wherein said sensing node of said charge coupled device stage comprises a floating node and said charge coupled device stage comprises a transfer gate between said floating node and said photogate;
• a drain diffusion connected to a drain bias voltage;
• a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal;
• wherein said readout circuit further comprises a double correlated sampling circuit comprising:
• a pair of sample and hold field effect transistors formed in said substrate, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said output transistor;
• a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors;
• means for sensing a potential of each of said sample and hold capacitors at respective intervals;
• wherein said focal plane array of cells is organized by rows and columns of said cells, and wherein said means for sensing comprises:
• a row select field effect transistor formed in said substrate having its source and drain connected between said source of said source follower transistor and said pair of sample and hold transistors and a gate connected to a row select signal;
• a pair of sample and hold output transistors having respective gates and sources connected across respective ones of said pair of sample and hold capacitors, and having respective drains;
• respective differential output nodes of said correlated double sampling circuit;
• and
• a pair of column select transistors formed in said substrate each having a source and drain connected between a drain of a respective one of said sample and hold output transistors and a gate connected to a column select signal.