Digital phase-locked loop arrangement for use in a desynchronizer

Digital phase locked loop arrangement for use in a desynchronizer, comprising:

• a low pass filter (LPF), responsive to a corrected read/write address difference signal, for providing a low pass filtered signal;
• an oscillator (OSC), responsive to the low pass filtered signal for providing a read address signal (RDADDR);
• a subtracter (S1), responsive at a positive input thereof to a write address signal (WRADDR) and at a negative input thereof to the read address signal, for providing a read/write address difference signal;
• a gapped clock (CLK1), responsive to a pattern adaptation signal, for providing a gapped clock stream normally constituted by consecutive like patterns each comprising pulses and gaps;
• a control (CTRL) having a control signal generator means, responsive to a bitstream (BITSTR), for providing at least a first control signal (V1/V2) and having a control means, responsive to the first control signal (V1/V2), for providing the pattern adaptation signal for adapting said patterns of said gapped clock stream;
• a counter means (CTR), responsive to the gapped clock stream, for providing the write address signal (WRADDR);
• wherein said digital phase locked loop arrangement further comprises:
• a second subtracter (S2), responsive at a positive input thereof to the read/write address difference signal, and responsive at a negative input thereof to a correction value signal (CORRV1), for providing the corrected read/write address difference signal;
• a second clock (CLK2) for providing a second clock signal having a second rate;
• and
• a correction means (CORR) including a first correction circuit, responsive to the first control signal (V1/V2) and to the second clock (CLK2) signal, for providing the correction value signal (CORRV1) which is varied to zero at the second rate of the second clock (CLK2) and which is varied with a predetermined value in response to the first control signal (V1/V2).