Soft symbol decoding

A method of generating a soft symbol for use in decoding a received digital signal into bits that are ones and zeroes, the soft symbol being generated from bits of a binary representation of a branch metric, the method comprising the steps of:

• generating a hard decision bit associated with a state;
• concatenating the ones complement of a preselected first number of bits of a binary representation of the branch metric with the hard decision bit to form the soft symbol when the hard decision bit is one;
• and
• concatenating a preselected second number of bits of a binary representation of the branch metric with a hard decision bit to form the soft symbol when the hard decision bit is not one.

A circuit for generating a binary soft symbol for use in decoding a received digital signal into bits that are ones and zeroes, the circuit comprising:

• means for receiving a hard decision bit, the hard decision bit associated with a state;
• means for storing a binary representation of a branch metric associated with the state;
• a plurality of exclusive OR gates corresponding in number to predetermined number of bits of the binary representation of the branch metric associated with the state, each of the plurality of exclusive OR gates having a first input to receive a bit of the binary representation of the branch metric, a second input to receive the hard decision bit, and an output, the output of the plurality of exclusive OR gates collectively providing the least significant bits of a soft symbol;
• and
• means for providing the hard decision bit as the most significant bit of the soft symbol.

A receiver for decoding a sequence of received symbols into bits that are ones and zeroes using soft symbol decoding, comprising:

• means for receiving a sequence of symbols transmitted over a transmission channel;
• means, responsive to the means for receiving, for calculating a branch metric for a possible transition from an individual state at one symbol instant to an individual state at a next symbol instant, the branch metric having a binary representation;
• means for receiving a hard decision bit associated with one of said symbol instants;
• a plurality of exclusive OR gates corresponding in number to a predetermined number of bits of the binary representation of the branch metric associated with the next symbol instant, each of the plurality of exclusive OR gates having a first input to receive a bit of the binary representation of the branch metric, a second input to receive the hard decision bit, and an output, the output of the plurality of exclusive OR gates collectively providing the least significant bits of a soft symbol;
• and
• means for providing the hard decision bit as the most significant bit of the soft symbol, whereby said soft symbol is generated from said branch metric for use in the decoding.

A circuit for generating a binary soft symbol for use in a decoding a received digital signal into bits that are ones and zeroes, the circuit comprising:

• circuitry for receiving a hard decision bit, the hard decision bit associated with a state;
• a register for storing a binary representation of a branch metric associated with the state;
• a plurality of logic circuits corresponding in number to a predetermined number of bits of the binary representation of the branch metric associated with the state, each of the plurality of logic circuits having a first input to receive a bit of the binary representation of the branch metric, a second input to receive the hard decision bit, and an output, the output of the plurality of logic circuits collectively providing the least significant bits of a soft symbol;
• and
• circuitry for providing the hard decision bit as the most significant bit of the soft symbol.