US 5,471,485 AGranted

Reed-solomon decoder using discrete time delay in power sum computation

AssigneeLSI Logic Corporation

InventorPo Tong

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Abstract

A power sum computation unit for a Reed-Solomon decoder having r redundant symbols and in which a code word, R, has a first plurality (n) of symbols, each symbol having a plurality (m) of bits, including multiplier unit for multiplying in parallel M symbols by powers of a finite field element, .alpha., to obtain the power sums ##EQU2## The multiplier unit includes M multipliers for multiplying M symbols by powers of alpha, and memory delay including a latch, a random access memory, and a flipflop store symbols and sequentially provide M symbols to the multiplier unit. Exclusive OR gate selectively connects products from the multiplier unit and data input words to the memory delay. A counter is provided for the random access memory with the counter having a modulo number equal to one less than r/M, and the random access memory having a depth equal to one less than r/M.

Claims5

Dependent claims

A power sum computation unit for a decoder of a Reed-Solomon code having a redundancy of r symbols and m bits per symbol in which M parallel multipliers operate on M symbols simultaneously to increase computation speed by M over a symbol-serial computation speed, said power sum computation unit comprising

data input means for sequentially receiving coded symbols,
a plurality of exclusive OR gates equal in number to said plurality of multipliers,
memory delay means having a bit width equal in number to said number of multipliers times the number of bits per symbol, and a depth equal in number to said redundancy divided by the number of multipliers,
said plurality of exclusive OR gates connecting coded symbols to said memory delay means,
multiplication means including said M parallel multipliers,
gate means for sequentially applying said symbols stored in said memory delay means to said M parallel multipliers,
means for providing powers of a finite field element, .alpha., from the power 0 to the power equal in number to one less than the redundancy to said multiplication means, whereby said multiplication means multiplies in parallel M symbols by said powers of said alpha, and
means for applying the products from said multiplications means to said exclusive OR gates along with coded symbols to provide a power sum output from said exclusive OR gate.

5 more elements

Dependencies are inferred from the claim text.