US 5,471,481 AGranted

Testing method for electronic apparatus

AssigneeSony Corporation

InventorsKoji Okumoto, Katsumi Matsuno, Toru Shiono, Toshitaka Senuma, Tokuya Fukuda, Shinji Takada

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Abstract

A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.

Claims15

Dependent claims

A method of testing the interconnection of first and second integrated circuits each including a parallel data input/output terminal, serial input and output terminals, and boundary scan cells associated with said parallel data input/output terminal, said first and second integrated circuits each selectively having a test mode in which the respective serial input and output terminals are operable to receive and supply test serial data and a non-test mode in which said serial input and output terminals are operable to receive and supply non-test serial data, and said parallel data input/output terminal of said first integrated circuit being connected to said parallel data input/output terminal of said second integrated circuit, the method comprising the steps of:

selectively setting said first and second integrated circuits in said test mode and said non-test mode;
supplying test data to said serial input terminal of said first integrated circuit when said first integrated circuit is in said test mode;
controlling said first integrated circuit to serially store said test data in said boundary scan cells and to supply the test data stored in said boundary scan cells as parallel data from said first integrated circuit at said parallel data input/output terminal;
controlling said second integrated circuit to store in its boundary scan cells said parallel data supplied to its parallel data input/output terminal from said parallel data input/output terminal of said first integrated circuit, and to serially supply the parallel data stored in said boundary scan cells as output test data from said second integrated circuit at its serial output terminal;
and
comparing the output test data supplied from said serial output terminal of said second integrated circuit with said test data supplied to said serial input terminal of said first integrated circuit as an indication of the state of said interconnection between said first and second integrated circuits.

3 more elements

The combination of first and second integrated circuits each including a parallel data input/output terminal, serial input and output terminals, and boundary scan cells associated with said parallel data input/output terminal, said first and second integrated circuits each having a test mode in which the respective serial input and output terminals are operable to receive and supply test serial data and a non-test mode in which said serial input and output terminals are operable to receive and supply non-test serial data, and means connecting said parallel data input/output terminal of said first integrated circuit to said parallel data input/output terminal of said second integrated circuit;

and apparatus for testing interconnections of said first and second integrated circuits, comprising:
means for selectively setting said first and second integrated circuits in said test mode and said non-test mode;
means operable in said test mode for supplying test data to said serial input terminal of said first integrated circuit;
first control means operable in said test mode for causing said first integrated circuit to serially store said test data in its boundary scan cells and to supply the test data stored in its boundary scan cells as parallel data from said first integrated circuit at its parallel data input/output terminal;
second control means operable in said test mode for causing said second integrated circuit to store in its boundary scan cells said parallel data supplied to its parallel data input/output terminal from said parallel data input/output terminal of said first integrated circuit, and to serially supply the parallel data stored in said boundary scan cells as output test data from said second integrated circuit at its serial output terminal;
and
means for comparing the output test data supplied from said serial output terminal of said second integrated circuit with said test data supplied to said serial input terminal of said first integrated circuit as an indication of the state of said interconnection between said first and second integrated circuits.

4 more elements

Dependencies are inferred from the claim text.