Arrangement for column sparing of memory

A memory replacement arrangement for replacing faulty memory elements in a memory array and said memory array including M-rows X N-columns including one replacement column, an Nth column, of memory elements, said memory array including said replacement column of memory elements coupled to a computer via address and data buses, said memory replacement arrangement comprising:

• transceiver means coupled between said computer and said memory array, said transceiver means for selectively coupling said memory elements of said memory array to said computer via said data bus;
• enabling means coupled to said transceiver means and to said computer via said address bus, and for said faulty memory elements, said enabling means selectively replacing said faulty memory elements in different columns in each of said M-rows of said memory array enabling said transceiver means to couple a plurality of memory elements from said M-rows and from (N-1) columns of said different columns including at least one replacement memory element in a selectable column in any of said M-rows to said computer for transferring a selected computer word into or out of said memory array;
• said enabling means including:
• address decoding means coupled to said computer via said address bus, said address decoding means generating a plurality of chip selects from an address transmitted from said computer, said chip selects enabling said M rows of memory elements of said memory array;
• and
• direction and enable decoding means coupled to said computer via said address bus, and to said memory array, said direction and enable decoding means producing a plurality of enable signals for selectively enabling said transceiver means to select (N-1) of said columns of memory elements of said different columns of memory elements including said plurality replacement memory elements.