Semiconductor memory device having address transition and supply voltage detecting circuits
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroyasu Makihara
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Abstract
A ROM includes an address transition detection circuit and a supply voltage rising detection circuit. The supply voltage rising detection circuit inhibits an operation of the address transition detection circuit until a supply voltage reaches a predetermined voltage after application of power.
Claims13
A semiconductor memory device driven by a supply voltage comprising:
- detecting means for detecting transition of an address signal to generate a detection signal;
- read only memory means which operates in response to said address signal and said detection signal for reading out data;
- and
- inhibiting means for inhibiting an operation of said detecting means until the supply voltage reaches a predetermined voltage after application of power such that said detection signal is generated only after the supply voltage has reached the predetermined voltage.
A method for operating a semiconductor memory device driven by a supply voltage comprising the steps of:
- detecting transition of an address signal and generating a detection signal;
- reading out data stored in read only memory means in response to said address signal and said detection signal;
- generating an inhibiting signal until said supply voltage reaches a predetermined voltage after application of power;
- and
- inhibiting generation of said detection signal in response to said inhibiting signal such that said detection signal is generated only after the supply voltage has reached the predetermined voltage.
An address transition detecting device for detecting transition of an address signal including:
- detecting means for detecting the transition of said address signal and generating a detection signal to read out data stored in a read only memory means;
- and
- inhibiting means for inhibiting an operation of said detecting means until a supply voltage reaches a predetermined voltage after application of power such that said detection signal is generated only after the supply voltage has reached the predetermined voltage.
An address transition detecting method comprising the steps of:
- detecting transition of an address signal and generating a detection signal for reading out data stored in a read only memory means;
- and
- inhibiting generation of said detection signal until a power supply voltage reaches a predetermined voltage after application of power such that said detection signal is generated only after the supply voltage has reached the predetermined voltage.
A semiconductor memory device driven by a power supply voltage comprising:
- a) detecting means for detecting transition of an address signal to generate a detection signal;
- b) read only memory means which operates in response to said address signal and said detection signal for reading out data;
- and
- c) inhibiting means for inhibiting an operation of said detection means until the power supply voltage reaches a predetermined voltage after application of power such that said detection signal is generated only after the supply voltage has reached the predetermined voltage, wherein said inhibiting includes
- i) a first power supply terminal for receiving said supply voltage,
- ii) a second power supply terminal for receiving a ground voltage,
- iii) a node,
- iv) a first field effect element which is connected between said first power supply terminal and said node and is always turned on,
- v) a second field effect element which is diode-connected between said second power supply terminal and said node, and
- vi) inverting means, coupled to said node, for inverting a signal at said node to supply said output signal to said detecting means.
An addressable semiconductor memory device driven by a supply voltage sourse and responsive to address signals for storing data, comprising:
- first means for detecting a transition of an address signal;
- second means for detecting that the supply voltage source has attained a prescribed voltage level following turning on of the source;
- a read only memory for storing data at a location prescribed by the address signal;
- and
- third means for reading out said data in said memory in accordance with outputs of said first and second means,
- such that said data is read out from said memory upon an address signal transition only after the supply voltage source has attained said prescribed voltage level.
Dependencies are inferred from the claim text.