Test circuit for refresh counter of clock synchronous type semiconductor memory device

A synchronous semiconductor memory device taking in external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:

• a plurality of banks each having a plurality of dynamic memory cells requiring refresh operations, said banks being activated independently of each other;
• an address counter for generating a refresh address specifying memory cells of said memory cells and a bank out of said banks to be refreshed;
• refresh means for refreshing the memory cells of the bank specified by said refresh address generated from said address counter in response to a refresh designating signal;
• and
• initialization means for initializing at least a bank address specifying one of said banks in said refresh address being generated from said address counter at an address specifying a prescribed one of said banks.

A synchronous semiconductor device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of dynamic type memory cells arranged in rows and columns;
• refresh mode detection means responsive to a refresh designating signal applied in synchronization with said clock signal for detecting that a refresh mode of operation is designated to generate a refresh mode detecting signal;
• refresh address generation means responsive to said refresh mode detecting signal for generating a refresh address signal designating a row of memory cells to be refreshed in said memory cell array;
• refresh means responsive to said refresh mode detecting signal and said refresh address signal for refreshing data of the row of memory cells;
• and
• setting means responsive to an operation mode indicating signal indicating a particular operation mode, for determining a timing at which said refresh means is disabled to terminate the refreshing of data of said row of memory cells.

A synchronous semiconductor memory device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of dynamic type memory cells arranged in rows and columns;
• row selection means responsive to an applied row address signal for selecting a row of memory cells in said memory cell array;
• an address generation means responsive to a refresh designating signal applied in synchronization with said clock signal, for generating and applying a refresh address signal designating a row of memory cells to be refreshed to said row selection means;
• enabling means responsive to a counter check mode indicating signal indicating an operation mode in which whether said address generation means correctly operates to generate refresh addresses should be checked, for allowing said column selection means to select a column in said memory cell array in accordance with an external address signal.

A synchronous semiconductor memory device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• refresh address generation means responsive to a refresh designating signal for generating a refresh address signal specifying a row of memory cells on said memory cell array;
• refresh means responsive to said refresh designating signal for refreshing data of said row of memory cells specified by said refresh address signal;
• and
• resetting means responsive to a predetermined operation mode indicating signal for resetting a refresh address signal to be generated from said refresh address generation means to a predetermined initial value.

A synchronous semiconductor device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of dynamic type memory cells arranged in rows and columns;
• refresh mode detection means responsive to a refresh designating signal applied in synchronization with said clock signal for detecting that a refresh mode of operation is designated to generate a refresh mode detecting signal;
• refresh address generation means responsive to said refresh mode detecting signal for generating a refresh address signal designating a row of memory cells to be refreshed in said memory cell array;
• refresh means responsive to said refresh mode detecting signal and said refresh address signal for refreshing data of the row of memory cells;
• setting means responsive to an operation mode indicating signal indicating a particular operation mode, for determining a timing at which said refresh means is disabled to terminate the refreshing of data of said row of memory cells;
• column selection inhibition means responsive to said refresh mode designating signal for inhibiting an operation of selecting a column in said columns in accordance with a column address signal applied in synchronization with said clock signal;
• and
• release means responsive to said refresh mode indicating signal for setting free the column selection operation inhibited by said column selection inhibition means to allow external access to a memory cell designated by said refresh address signal and said column address signal when said refresh mode indicating signal is active.

A synchronous semiconductor device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of dynamic type memory cells arranged in rows and columns;
• refresh mode detection means responsive to a refresh designating signal applied in synchronization with said clock signal for detecting that a refresh mode of operation is designated to generate a refresh mode detecting signal;
• refresh address generation means responsive to said refresh mode detecting signal for generating a refresh address signal designating a row of memory cells to be refreshed in said memory cell array;
• refresh means responsive to said refresh mode detecting signal and said refresh address signal for refreshing data of the row of memory cells;
• and
• setting means responsive to an operation mode indicating signal indicating a particular operation mode, for determining a timing at which said refresh means is disabled to terminate the refreshing of data of said row of memory cells, wherein said operation mode indicating signal designates a counter check mode operation in which it is checked whether said refresh address generation means correctly operates to generate said refresh address signal.

A synchronous semiconductor device operating in synchronization with a clock signal, comprising:

• a memory cell array having a plurality of dynamic type memory cells arranged in rows and columns;
• refresh mode detection means responsive to a refresh designating signal applied in synchronization with said clock signal for detecting that a refresh mode of operation is designated to generate a refresh mode detecting signal;
• refresh address generation means responsive to said refresh mode detecting signal for generating a refresh address signal designating a row of memory cells to be refreshed in said memory cell array;
• refresh means responsive to said refresh mode detecting signal and said refresh address signal for refreshing data of the row of memory cells;
• and
• setting means responsive to an operation mode indicating signal indicating a particular operation mode, for determining a timing at which said refresh means is disabled to terminate the refreshing of data of said row of memory cells, wherein said setting means includes
• disabling means responsive to said refresh mode detecting signal for disabling said refresh means after elapse of a predetermined time period since generation of said refresh mode detecting signal,
• operation mode detecting means in response to said operation mode detecting signal for detecting that said particular operation mode is designated and for inhibiting said disabling means from operation,
• termination mode detection means responsive to a precharge indicating signal designating that a memory cell selected in said memory cell array should be brought into a non-selected state in a stand-by state, and
• termination means responsive to said disabling means and termination mode detection means for disabling said refresh means to terminate the refreshing of data of said row of memory cells designated by said refresh address signal.