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US 5,471,429 AGranted
Burn-in circuit and method therefor of semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Keun Lee, Choong-Keun Kwak
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AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Keun Lee, Choong-Keun Kwak
Estimating the term…
The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM. The semiconductor memory device according to the present invention, which includes a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, and a column decoder for selecting the column of the memory cell array, comprises an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, and a burn-in control circuit for inputting the output signal of the read/write control circuit, supplying a burn-in signal responsive to the data input through the input/output line control circuit to the row decoder and column decoder, and enabling a burn-in test of the same chip after a package process.
A semiconductor memory device including a memory cell array which has a plurality of memory cells that are accessed in response to an address which is provided to row and column decoders, said semiconductor memory device comprising:
A semiconductor memory device including a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, a column decoder for selecting the column of the memory cell array, an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, and a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, said device comprising:
A semiconductor memory device including a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, a column decoder for selecting the column of the memory cell array, an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, and a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, said device comprising:
A burn-in method of a semiconductor memory device including a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, a column decoder for selecting the column of the memory cell array, an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, and a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, said method comprising the steps of:
A burn-in method of a semiconductor memory device including a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, a column decoder for selecting the column of the memory cell array, an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, and a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, said method comprising the steps of:
Dependencies are inferred from the claim text.