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AssigneeFujitsu Limited
InventorsFuminori Yumitori, Yasuhiro Fujii
Estimating the term…
The present invention relates to a high-speed data transmission system for efficiently transmitting large amounts of data within short periods of time. A DRAM comprises at least a memory cell, sense amplifiers, a /RAS signal input, a word line (WL) boost signal generator, a sense amplifier control signal-generator, and a sense amplifier drive signal-generator, wherein the memory cell is constituted by a plurality of banks, the sense amplifiers are provided in a corresponding plurality of numbers, the sense amplifier control signal-generator are provided in a plurality of numbers to correspond to the plurality of banks, and provision is made of external sense amplifier activating signal terminals which are connected to the sense amplifier control signal-generator in order to activate the sense amplifiers independently of the /RAS signal.
A dynamic random access memory (DRAM) comprising:
A dynamic random access memory (DRAM) comprising:
Dependencies are inferred from the claim text.