Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• a plurality of semiconductor layers of a first conductivity type, said semiconductor layers extending parallelly in a column direction and being isolated from each other;
• a plurality of memory cells disposed in a matrix of columns and rows, each memory cell having source and drain regions of a second conductivity type different from said first conductivity type, a channel region formed between said source and drain regions and a gate structure formed on the channel region with a gate insulating layer interposed therebetween and including a floating gate, an interlayer insulating layer and a control gate, said memory cells being divided into a plurality of memory cell groups formed on the semiconductor layers, respectively, so that all the memory cells included in one of said memory cell groups are formed on one of the semiconductor layers respectively and drain-source circuits of the memory cells of each group are connected in series to provide a series electrical path;
• a plurality of first bit lines provided to said plurality of memory cell groups, respectively, each first bit line being connected to the semiconductor layer on which the memory cells included in an associated one of said plurality of memory cell groups are formed;
• a plurality of second bit lines provided to said plurality of memory cell groups, respectively, each second bit line being connected to one end of the series electrical path provided to the memory cells included in an associated one of said plurality of memory cell groups:
• and
• a plurality of word lines, each word line being connected to the control gates of the memory cells disposed in one of the rows.