Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
AssigneeSun Microsystems, Inc.
InventorsJames W. Rose, Godfrey P. D'Souza, Jonathan J. Stinehelfer, James F. Testa
Life of this patent
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Abstract
A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
Claims23
A memory device, comprising:
- a storage cell having a storage node for holding a logic state indicative of a first data value;
- a bit line associated with the storage cell;
- a pass transistor coupled to the bit line and the storage node of the storage cell;
- a reverse-biasing circuit, coupled to the pass transistor, for reverse-biasing the pass transistor regardless of whether the storage node is maintained at a logical 1 or a logical 0.
A method of providing a memory device, comprising the steps of:
- providing a storage cell having a storage node for holding a logic state indicative of a data value;
- providing a bit line associated with the storage cell;
- providing a pass transistor coupled to the bit line and the storage node of the storage cell;
- and
- providing a reverse-biasing circuit, coupled to the pass transistor, for reverse-biasing the pass transistor regardless of whether the storage node is maintained at a logical 1 or a logical 0.
A method of operating a memory cell including a storage node for holding a logic state indicative of a data value, a bit line associated with the memory cell, and a pass transistor coupled between the storage node and the bit line, comprising the steps of:
- maintaining the pass transistor in a substantially reversed-biased state regardless of whether the storage node is maintained at a logical 1 or a logical O.
Dependencies are inferred from the claim text.