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US 5,471,415 AGranted
Cache tag memory
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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Abstract
A comparator system for a cache tag RAM memory that makes use of data bus lines already available on the cache tag RAM. The true data bus lines are connected together at a connection point and form a "wired" connection or configuration. A "wired" connection may be for example, a "wired OR" "wired NOR" "wired AND" or "wired NAND" according to the present invention. The complement data bus lines on the cache tag RAM are connected in a similar fashion. The comparator system is connected to the cache tag RAM data bus lines and generates a hit or miss signal based on the data on the cache tag RAM data bus lines and input data that controls transistors connected to the cache tag RAM data bus lines, resulting in a faster comparison function.
Claims26
A digital computer system comprising:
- a processor
- a main memory;
- a data cache connected to the processor and the main memory;
- a true data signal and a complement data signal;
- and
- a tag cache memory connected to the processor and the main memory, the tag cache memory including:
- a plurality of memory groups, each memory group having a plurality of true and complement outputs;
- a plurality of true and complement data bus lines, wherein each true data bus line is connected to a true output from each of the plurality of memory groups, each complement data bus line is connected to a complement output from each of the plurality of subgroups, and the true and complement data bus lines having the true and complement data signals, respectively;
- a plurality of data bus circuits, each data bus circuit including:
- a true circuit input and a complement circuit input, wherein the true and complement circuit inputs are connected to a true and complement data bus line;
- a true circuit output and a complement circuit output;
- a first transistor, having a drain connected to the true circuit input, a source connected to a power supply voltage, and a gate connected to the complement data signal;
- and
- a second transistor having a drain connected to the complement circuit input, a source connected to the power supply voltage, and a
- gate connected to the true data signal;
- and a compare circuit having a plurality of input pairs, each input pair having a true input and a complement input, and an output for indicating the presence of a hit, wherein true input of each input pair is connected to the true circuit input of a data bus circuit and the complement input of each input pair is connected to the complement circuit input of the data bus circuit, wherein the presence of a hit may be indicated at the output of the compare circuit.
13 more elements
A cache tag memory comprising:
- a plurality of memory groups, each memory group having a plurality of true and complement outputs;
- a plurality of true and complement data bus lines, wherein each true data bus line is connected to a true output from each of the plurality of memory groups, each complement data bus line is connected to a complement output from each of the plurality of groups, and the true and complement data bus lines having the true and complement data signals, respectively;
- a plurality of data bus circuits, each data bus circuit including:
- a true circuit input and a complement circuit input, wherein the true and complement circuit inputs are connected to a true and complement data bus line;
- a true circuit output and a complement circuit output;
- a first transistor having a drain connected to the true circuit input, a source connected to a power supply voltage, and a gate connected to the complement data signal;
- and
- a second transistor having a drain connected to the complement circuit input, a source connected to the power supply voltage, and a gate connected to the true data signal;
- and
- a compare circuit having a plurality of input pairs, each input pair having a true input and a complement input, and an output for indicating the presence of a hit, wherein true input of each input pair is connected to the true circuit input of a data bus circuit and the complement input of each input pair is connected to the complement circuit input of the data bus circuit, wherein the presence of a hit may be indicated at the output of the compare circuit.
7 more elements
A cache tag RAM compare circuit comprising:
- a plurality of true and complement data bus lines, wherein each true data bus line has a first transistor, having a drain connected to the true data bus line, a source connected to a first power supply voltage, and a gate connected to a complement data input and wherein each complement data bus line has a second transistor having a drain connected to the complement data bus line, a source connected to the first power supply voltage, and a gate connected to the data input;
- a comparison circuit, the comparison circuit having a plurality of input pairs, each input pair having a true input and a complement input, and an output for indicating the presence of a hit, wherein true input of each input pair is connected to a true data bus line and the complement input of each input pair is connected to a complement data bus line, wherein the presence of a hit may be indicated at the output of the comparison circuit.
Dependencies are inferred from the claim text.