Recycling and parallel processing method and apparatus for performing discrete cosine transform and its inverse

A one-dimensional discrete cosine transform (DCT) apparatus for performing a six-stage DCT fast algorithm to parallel process a sequence of input data of an 8.times.8 data block so as to generate a sequence of transform data, said DCT fast algorithm including first, third and fifth stages, each of which involving a plurality of butterfly operations, second and fourth stages, each of which involving a plurality of post-addition multiplication operations, and a sixth stage involving a plurality of intrinsic multiplication operations, said DCT apparatus comprising:

• an input unit receiving said input data;
• a butterfly operation unit controllable so as to perform said first, third and fifth stages of said DCT fast algorithm and so as to generate respectively first-, third- and fifth-stage output data when performing said first, third and fifth stages of said DCT algorithm;
• a multiplication operation unit controllable so as to perform said second, fourth and sixth stages of said DCT fast algorithm and so as to generate respectively second-, fourth- and sixth-stage output data when performing said second, fourth and sixth stages of said DCT fast algorithm;
• a data register unit connected to said butterfly operation unit and said multiplication operation unit and controllable so as to store said first-, second-, third-, fourth- and fifth-stage output data therein;
• a control unit connected to said input unit, said butterfly operation unit, said data register unit and said multiplication operation unit;
• said control unit controlling said input unit to provide said input data to said butterfly operation unit in order to enable said butterfly operation unit to perform said first stage of said DCT fast algorithm;
• said control unit further controlling said data register unit to store said first-stage output data from said butterfly operation unit therein;
• said control unit further controlling said data register unit to provide predetermined ones of said first-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said second stage of said DCT fast algorithm when said predetermined ones of said first-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said first-stage of said DCT fast algorithm;
• said control unit further controlling said data register unit to store said second-stage output data from said multiplication operation unit therein;
• said control unit further controlling said data register unit to provide said first- and second-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said third stage of said DCT fast algorithm after said butterfly operation unit has finished performing said first stage of said DCT fast algorithm;
• said control unit further controlling said data register unit to store said third-stage output data from said butterfly operation unit therein;
• said control unit further controlling said data register unit to provide predetermined ones of said third-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said fourth stage of said DCT fast algorithm when said predetermined ones of said third-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said third-stage of said fast DCT algorithm;
• said control unit further controlling said data register unit to store said fourth-stage output data from said multiplication operation unit therein;
• said control unit further controlling said data register unit to provide said third- and fourth-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said fifth stage of said DCT fast algorithm after said butterfly operation unit has finished performing said third sage of said DCT fast algorithm;
• said control unit further controlling said data register unit to store said fifth-stage output data from said butterfly operation unit therein;
• said control unit further controlling said data register unit to provide said fifth-stag output data to said multiplication operation unit in order to enable said multiplication operation unit to perform said sixth stage of said DCT fast algorithm;
• and
• an output unit connected to said multiplication operation unit and said control unit and controlled by said control unit so as to receive said sixth-stage output data from said multiplication operation unit.

An inverse discrete cosine transform (IDCT) method using a six-stage IDCT fast algorithm for parallel processing a sequence of input data of an 8.times.8 data block so as to generate a sequence of transform data, said IDCT fast algorithm including a first stage involving a plurality of intrinsic multiplication operations, second, fourth and sixth stages, each of which involving a plurality of butterfly operations, and third and fifth stages, each of which involving a plurality of post-multiplication subtraction operations, said IDCT method comprising the steps of:

• (a) providing an input unit to receive said input data;
• (b) controlling said input unit to provide said input data to a multiplication operation unit in order to enable said multiplication operation unit to perform said first stage of said IDCT fast algorithm;
• (c) controlling a data register unit to store first-stage output data from said multiplication operation unit therein;
• (d) controlling said data register unit to provide said first-stage output data to a butterfly operation unit in order to enable said butterfly operation unit to perform said second stage of said IDCT fast algorithm;
• (e) controlling said data register unit to store second-stage output data from said butterfly operation unit therein;
• (f) controlling said data register unit to provide predetermined ones of said second-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said third stage of said IDCT fast algorithm when said predetermined ones of said second-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said second stage of said IDCT fast algorithm;
• (g) controlling said data register unit to store third-stage output data from said multiplication operation unit therein;
• (h) controlling said data register unit to provide said second- and third-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said fourth stage of said IDCT fast algorithm after said butterfly operation unit has finished performing said second stage of said IDCT fast algorithm;
• (i) controlling said data register unit to store fourth-stage output data from said butterfly operation unit therein;
• (j) controlling said data register unit to provide predetermined ones of said fourth-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said fifth stage of said IDCT fast algorithm when said predetermined ones of said fourth-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said fourth stage of said IDCT fast algorithm;
• (k) controlling said data register unit to store fifth-stage output data from said multiplication operation unit therein;
• (l) controlling said data register unit to provide said fourth- and fifth-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said sixth stage of said IDCT fast algorithm after said butterfly operation unit has finished performing said fourth stage of said IDCT fast algorithm;
• and
• (m) controlling an output unit to receive sixth-stage output data from said butterfly operation unit.

A one-dimensional inverse discrete cosine transform (IDCT) apparatus for performing a six-stage IDCT fast algorithm to parallel process a sequence of input data of an 8.times.8 data block so as to generate a sequence of transform data, said IDCT fast algorithm including a first stage involving a plurality of intrinsic multiplication operations, second, fourth and sixth stages, each of which involving a plurality of butterfly operations, and third and fifth stages, each of which involving a plurality of post-multiplication subtraction operations, said IDCT apparatus comprising:

• an input unit receiving said input data;
• a multiplication operation unit controllable so as to perform said first, third and fifth stages of said IDCT fast algorithm and so as to generate respectively first-, third- and fifth-stage output data when performing said first, third and fifth stages of said IDCT fast algorithm;
• a butterfly operation unit controllable so as to perform said second, fourth and sixth stages of said IDCT fast algorithm and so as to generate respectively second-, fourth- and sixth-stage output data when performing said second, fourth and sixth stages of said IDCT fast algorithm;
• a data register unit connected to said butterfly operation unit and said multiplication operation unit and controllable so as to store said first-, second-, third-, and fifth-stage output data therein;
• a control unit connected to said input unit, said butterfly operation unit, said data register unit and said multiplication operation unit;
• said control unit controlling said input unit to provide said input data to said multiplication operation unit in order to enable said multiplication operation unit to perform said first stage of said IDCT fast algorithm;
• said control unit further controlling said data register unit to store said first-stage output data from said multiplication operation unit therein;
• said control unit further controlling said data register unit to provide said first-stage output data to said butterfly operation unit in order to enable said butterfly operation unit to perform said second stage of said IDCT fast algorithm;
• said control unit further controlling said data register unit to store said second-stage output data from said butterfly operation unit therein;
• said control unit further controlling said data register unit to provide predetermined ones of said second-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said third stage of said IDCT fast algorithm when said predetermined ones of said second-stage output data have been stored in said data register unit, while said butterfly operation unit continues to perform said second stage of said IDCT fast algorithm;
• said control unit further controlling said data register unit to store said third-stage output data from said multiplication operation unit therein;
• said control unit further controlling said data register unit to provide said second- and third-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said fourth stage of said IDCT fast algorithm after said butterfly operation unit has finished performing said second stage of said IDCT fast algorithm;
• said control unit further controlling said data register unit to store said fourth-stage output data from said butterfly operation unit therein;
• said control unit further controlling said data register unit to provide predetermined ones of said fourth-stage output data to said multiplication operation unit in order to enable said multiplication operation unit to begin performing said fifth stage of said IDCT fast algorithm when said predetermined ones of said fourth-stage output data have been stored in said data register unit, while Said butterfly operation unit continues to perform said fourth stage of said IDCT fast algorithm;
• said control unit further controlling said data register unit to store said fifth-stage output data from said multiplication operation unit therein;
• said control unit further controlling said data register unit to provide said fourth- and fifth-stage output data in a predetermined sequence to said butterfly operation unit in order to enable said butterfly operation unit to perform said sixth stage of said IDCT fast algorithm after said butterfly operation unit has finished performing said fourth stage of said IDCT fast algorithm;
• and
• an output unit connected to said butterfly operation unit and said control unit and controlled by said control unit so as to receive said sixth-stage output data from said butterfly operation unit.