US 5,471,411 AGranted

Interpolation filter with reduced set of filter coefficients

AssigneeAnalog Devices, Inc.

InventorsRobert W. Adams, Tom W. Kwan, Michael Coln

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Abstract

An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

Claims3

Dependent claims

a look-up table which maps the binary coefficient address to one of a plurality of regions of the address space, wherein an average first-order difference between adjacent filter coefficients corresponding to binary coefficient addresses in each region is substantially constant, wherein the look-up table has an input for receiving the binary coefficient address and an output providing an indication of the region corresponding to the binary coefficient address;
a shifter connected to receive a portion of the least significant bits of the binary coefficient address and for shifting the portion by an amount determined by the region indicated by the output of the look-up table to provide a shifter output;
means for combining the output of the look-up table with a portion of the most significant bits of the shifter output to produce an address N to access the memory element;
means for accessing the memory element to obtain a first coefficient ROM(N) from the smaller set using the address produced by the means for combining;
means for accessing the memory element to obtain a second coefficient ROM(N+1) from the smaller set using an address adjacent to the address produced by the means for combining;
means for generating an interpolation number INTERP, having a number K of bits from low-order bits of the shifter output;
and
means, connected to both the means for accessing and the means for generating, for performing a linear interpolation to obtain the desired filter coefficient wherein the desired filter coefficient is equal to ROM(N)+(ROM(N+1)-ROM(N))*(INTERP/2.sup.K).

5 more elements

An electronic device for producing a desired filter coefficient of a large set of filter coefficients for a digital filter, wherein each desired filter coefficient in the large set has a corresponding binary coefficient address in an address space defined by a number of taps of the digital filter, using a smaller set of coefficients stored in a memory element and a binary coefficient address in the address space and having a plurality of bits, wherein desired filter coefficients corresponding to only even addresses are stored in the memory element, and differences between adjacent filter coefficients in the memory element are stored in a difference memory, said electronic device comprising:

a look-up table which maps the binary coefficient address to one of a plurality of regions of the address space, wherein an average first-order difference between adjacent filter coefficients corresponding to binary coefficient addresses in each region is substantially constant, wherein the look-up table has an input for receiving the binary coefficient address and an output providing an indication of the region corresponding to the binary coefficient address;
a shifter connected to receive a portion of the bits of the least significant bits of the binary coefficient address and for shifting the portion by an amount determined by the region indicated by the output of the look-up table to provide a shifter output;
means for combining the output of the look-up table with a portion of most significant bits of the shifter output to produce an address N to access the memory element;
means for accessing the memory element to obtain a first coefficient ROM(N) from the smaller set using the address produced by the means for combining;
means for accessing the difference memory to obtain a difference DIFFROM(N) using the address produced by the means for combining;
means for generating an interpolation number INTERP, having a number K of bits from low-order bits of the shifter output;
and
means for performing a linear interpolation to obtain the desired filter coefficient wherein the desired filter coefficient is equal to ROM(N)+DIFF ROM(N)*(INTERP/2.sup.K), when the binary coefficient address is in between binary coefficient addresses corresponding to filter coefficients ROM(N) and ROM(N+1), and wherein the desired filter coefficient is equal to ROM(N)+DIFF ROM(N-1)*((INTERP/2.sup.K-1), when the binary coefficient address is in between binary coefficient addresses corresponding to filter coefficients ROM(N-1) and ROM(N).

5 more elements

Dependencies are inferred from the claim text.