A logic simulation apparatus, comprising:
- layout pattern data providing means for providing layout pattern data defining layout pattern of a logic circuit;
- data extracting means for extracting, on the basis of said layout pattern, circuit connection data defining relation of connections among elements constituting said logic circuit, circuit constant data of said elements, interconnection dimension data including dimension information of diffusion regions forming said elements and dimension information of interconnections among each element and divided power-supply line data including a divided power-supply line, in which a power-supply line from an external power-supply input terminal to said element is divided in branch point units, a length and a width thereof;
- process parameter providing means for providing a process parameter required in a process of manufacturing said logic circuit;
- power-supply information providing means for providing power-supply information including a power-supply voltage value and an internal resistance value of the external power-supply for operation of said logic circuit;
- gain coefficient calculating means for calculating a gain coefficient for each element of said logic circuit on the basis of said circuit constant data and said process parameter;
- parasitic capacitance value calculating means for calculating an interconnection parasitic capacitance value which is a capacitance value associated with each interconnection of said logic circuit on the basis of said circuit constant data, said interconnection dimension data and said process parameter;
- conduction current calculating means for calculating a conduction current value flowing when each element of said logic circuit turns on on the basis of said gain coefficient and said power-supply information;
- resistance value calculating means for calculating a voltage drop resistance value which is a sum of an interconnection resistance value of the power-supply line and said internal resistance value for each element of said logic circuit on the basis of said divided power-supply line data, said process parameter and said internal resistance value of said power-supply information;
- voltage drop value calculating means for calculating a voltage drop value occurring in the power-supply path extending from the external power-supply to said element when each said element of said logic circuit turns on on the basis of said power-supply voltage value of said power-supply information, said conduction current value and said voltage drop resistance value;
- signal propagation delay calculating means for calculating signal propagation delay time required for each said element of said logic circuit to propagate a logic signal on the basis of said gain coefficient, said interconnection parasitic capacitance and said voltage drop value;
- and
- logic simulation performing means for performing logic simulation on the basis of said circuit connection data and said signal propagation delay time.