US 5,471,398 A · MTOL software tool for converting an RTL behavioral model into layout information comprising bounding boxes and an associated interconnect netlist

Abstract

An MtoL software tool (FIG. 3) automates the process of converting an RTL behavioral model of the integrated circuit into corresponding layout information in a format that can be input directly to a floor planner/block router--the automated MtoL process facilitates iterative logic design including what-if analysis. A conventional RTL behavioral model is modified (40) to include MtoL bounding box and interconnect netlist macros. The resulting modified RTL module tree (42) is input to an MtoL extraction front-end (43) for conversion to an MtoL-formatted MtoL extract tree. A flattening transformation (44) on the hierarchical MtoL extract tree produces a non-hierarchical representation of the block structure together with a terminal interconnect netlist. The MtoL program then generates (45) MtoL layout information comprising a corresponding set of bounding boxes with terminal data and the associated interconnect netlist information, appropriately formatted for input to the floor planner/block router.

Claims12

Dependent claims

An MtoL (behavioral model to layout information) method for converting an RTL (register transfer level) behavioral model in the form of an RTL module tree including a plurality of hierarchical RTL modules representing the logic structure and functionality of an integrated circuit, into MtoL layout information for use in a block router, comprising the steps:

assigning to selected ones of the RTL modules MtoL macros that define corresponding geometric and terminal information;
extracting these MtoL macros along with the RTL modules for inclusion in the MtoL extract tree;
extracting from the RTL module tree the hierarchical RTL modules to create a corresponding hierarchical MtoL extract tree;
performing a flattening transformation of the hierarchical Mtol extract tree to provide a non-hierarchical representation including a terminal interconnection netlist, said performing said flattening transformation accomplished by the substeps of
performing a breadth first traversal through the hierarchical MtoL extract tree to create a linked list of all leaf nodes, which correspond to layout style blocks or intermediate blocks designated as leaf nodes, and
performing a depth first search of the Mtol extract tree to generate a netlist that describes a routine network;
and
using the non-hierarchical representation and terminal interconnect netlist, generating MtoL layout information.

5 more elements

assigning MtoL macros to selected ones of the RTL modules, said MtoL macros defining corresponding bounding box and terminal location information for said assigned RTL modules;
extracting from the RTL module tree the hierarchical RTL modules and MtoL macros to create a corresponding hierarchical MtoL extract tree;
performing a flattening transformation of the hierarchical Mtol extract tree to provide a non-hierarchical representation including a terminal interconnection netlist;
and
using the non-hierarchical representation and terminal interconnect netlist, generating MtoL layout information in the form of bounding boxes (including geometry and terminal location), initial bounding box placements, and an associated terminal interconnect netlist, said MtoL layout information generated for RTL modules not having assigned MtoL macros including said geometry and terminal location for bounding boxes having default bounding box geometries that is a smallest bounding box that Will accommodate a number of terminals assigned to said RTL module and a random distribution of terminal locations around said bounding box.

2 more elements

Dependencies are inferred from the claim text.

MTOL software tool for converting an RTL behavioral model into layout information comprising bounding boxes and an associated interconnect netlist

Life of this patent

MTOL software tool for converting an RTL behavioral model into layout information comprising bounding boxes and an associated interconnect netlist

Life of this patent

Abstract

Claims12