Glitchless frequency-adjustable ring oscillator

A clock generation circuit including:

• a reference clock putting out a stable reference clocking signal,
• a digital ring oscillator comprising:
• a series circuit loop of at least one inverting gate,
• a first delay line comprised of plural delays formed of digital transmission gates connected in series in a path between an output and an input of the inverting gate, and a clock output for providing a present adjustable clocking signal,
• a first multiplexer connected to taps along the first delay line for providing a coarse delay adjustment, and further comprising
• a second delay line formed of plural digital transmission gates in series with the first delay line within the series circuit loop and
• a second multiplexer connected to taps along the second delay line for providing a fine delay adjustment,
• clock monitoring circuitry connected to compare the clock output with the stable reference clocking signal and to produce a digital clock cycle count for each comparison made,
• programmed microcontroller means connected to receive the digital clock cycle count and to generate and put out a new tap selection value for controlling tap selection of the first multiplexer as a function of the digital clock cycle count and a desired clock output frequency set point, and
• synchronization means connected to the programmed microcontroller means and to the digital ring oscillator for synchronizing and applying the new tap selection value to the first multiplexer and to the second multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following application of the new tap selection value, the synchronization means providing a first control path for controlling tap selection in the first multiplexer, and for providing a second control path for controlling tap selection in the second multiplexer.

A clock generation circuit for generating a plurality of adjustable clocking signals including:

• a reference clock putting out a stable reference clocking signal,
• a plurality of digital ring oscillators, each ring oscillator being formed within an application specific integrated circuit and comprising:
• a series circuit loop of at least one inverting gate,
• a delay line comprised of plural delays formed of digital transmission gates connected in series in a path between an output and an input of the inverting gate, and a clock output for providing a present, adjustable clocking signal,
• a multiplexer connected to taps along the delay line for selecting among the taps, and
• clock monitoring circuitry connected to compare the clock output with the stable reference clocking signal and to produce a digital clock cycle count for each comparison made, and
• synchronization means connected to the digital ring oscillator for synchronizing and applying a new tap selection value to the multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following application of the new tap selection value,
• the application specific integrated circuit including a microprocessor interface means for connecting a supervisory programmed microcontroller to each one of the digital ring oscillators for enabling the application specific integrated circuit to be operatively interconnected with the supervisory programmed microcontroller,
• the supervisory programmed microcontroller being connected to the microprocessor interface means for receiving periodically from each ring oscillator the digital clock cycle count thereof and for periodically generating and putting out a new tap selection value for controlling tap selection of the first multiplexer as a function of the digital clock cycle count and a desired clock output frequency set point.

A glitchless, frequency adjustable ring oscillator circuit formed as one of a plurality of functions within a large scale digital integrated circuit and including an external reference frequency resonator means and a programmed digital microprocessor for controlling adjustment of frequency of the adjustable ring oscillator circuit, the large scale digital integrated circuit comprising:

• a reference clock connected to the external reference frequency resonator for generating and putting out a stable reference clocking signal,
• a series circuit loop of at least one inverting gate, a programmable delay line comprised of plural delays formed of digital transmission gates connected in series in a path between an output and an input of the inverting gate, there being a series of taps along the plurality of digital transmission gates, and a ring oscillator clock output for providing a present, adjustable clocking signal,
• at least a first multiplexer for selecting among the series of taps in accordance with a tap select control value,
• clock monitoring circuitry connected to compare the clock output with the stable reference clocking signal and to produce a digital clock cycle count for each comparison made,
• a synchronization circuit for generating and applying to the first multiplexer a tap switching control signal for synchronizing the tap select control value from the programmed digital microprocessor with the present, adjustable clocking signal, and with a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection without generating a glitch during multiplexer tap switching, and
• an interface for connecting the integrated circuit with the programmed digital microprocessor,
• the programmed digital microprocessor connected to the large scale integrated circuit via the interface and being programmed periodically to receive the digital clock cycle count and to generate and supply the tap select control value for controlling tap selection of the first multiplexer via the interface to the synchronization circuit, the tap select control value being developed by the microprocessor as a function of the digital clock cycle count and a programmed clock output frequency set point.

An adjustable ring oscillator circuit formed as one of a plurality of functions within a large scale digital integrated circuit and including an external reference frequency resonator means and a programmed digital microprocessor for controlling adjustment of frequency of the adjustable ring oscillator circuit, the large scale digital integrated circuit comprising:

• a reference clock connected to the external reference frequency resonator for generating and putting out a stable reference clocking signal,
• a series circuit loop of at least one inverting gate, a first programmable multi-tap delay line and a second programmable multi-tap delay line in a path between an output and an input of the inverting gate, and a ring oscillator clock output for providing a present, adjustable clocking signal,
• a first multiplexer for selecting among taps of the first programmable multi-tap delay line, and a second multiplexer for selecting among taps of the second programmable multi-tap delay line,
• clock monitoring circuitry connected to compare the clock output with the stable reference clocking signal and to produce a digital clock cycle count for each comparison made,
• the first delay line being formed of groups of plural transmission gates connected in tandem, each group providing a delay equal to an integral multiple of a unit delay period D, to which the first multiplexer is connected to provide a coarse delay adjustment, and the second delay line being formed of plural digital transmission gates in series with the first delay line within the series circuit loop, the second delay line digital transmission gates providing a unit delay period D between taps, and a second multiplexer connected to the taps along the second delay line for providing a fine delay adjustment,
• a synchronization circuit providing a first synchronized control path for controlling tap selection in the first multiplexer, and providing a second synchronized control path for controlling tap selection in the second multiplexer for synchronizing the tap select control value from the programmed digital microprocessor with the present, adjustable clocking signal, and with a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection, and
• an interface for connecting the integrated circuit with the programmed digital microprocessor,
• the programmed digital microprocessor connected to the large scale integrated circuit via the interface and being programmed periodically to receive the digital clock cycle count and to generate and supply the tap select control value for controlling tap selection of the first multiplexer via the interface to the synchronization circuit, the tap select control value being developed by the microprocessor as a function of the digital clock cycle count and a programmed clock output frequency set point.

An adjustable ring oscillator circuit formed as one of a plurality of functions within a large scale digital integrated circuit and including an external reference frequency resonator means and a programmed digital microprocessor for controlling adjustment of frequency of the adjustable ring oscillator circuit, the large scale digital integrated circuit comprising:

• a reference clock connected to the external reference frequency resonator for generating and putting out a stable reference clocking signal,
• a series circuit loop of at least one inverting gate, a programmable delay line comprised of plural delays formed of digital transmission gates connected in series in a path between an output and an input of the inverting gate, there being a series of taps along the plurality of digital transmission gates, and a ring oscillator clock output for providing a present, adjustable clocking signal,
• at least a first multiplexer for selecting among the series of taps in accordance with a tap select control value,
• clock monitoring circuitry connected to compare the clock output with the stable reference clocking signal and to produce a digital clock cycle count for each comparison made,
• a synchronization circuit for generating and applying to the first multiplexer a tap switching control signal for synchronizing the tap select control value from the programmed digital microprocessor with the present, adjustable clocking signal, and with a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection,
• the synchronization circuit including a plurality of flip-flops, there being a first flip-flop clocked in synchronism with the tap select control value supplied by the programmed microprocessor, and at least a second flip-flop clocked in synchronism with the present, adjustable clocking signal, for generating the tap switching control signal, and a control gate controlled by the tap switching control signal for gating the tap select control value to the first multiplexer, and
• an interface for connecting the integrated circuit with the programmed digital microprocessor,
• the programmed digital microprocessor connected to the large scale integrated circuit via the interface and being programmed periodically to receive the digital clock cycle count and to generate and supply the tap select control value for controlling tap selection of the first multiplexer via the interface to the synchronization circuit, the tap select control value being developed by the microprocessor as a function of the digital clock cycle count and a programmed clock output frequency set point.