US 5,471,172 AGranted

"AB Cascode" amplifier in an input stage of an amplifier or comparator

AssigneeNational Semiconductor Corporation

InventorsKwok-Fu Chiu, Don R. Sauer

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Abstract

An AB Cascode amplifier provides low quiescent current operation, while maintaining the high gain and wide bandwidth of prior art folded cascode amplifier. Instead of fixed current sources, the AB cascode amplifier uses variable current sources, which are biased by a fixed small current source and two variable biased transistor.

Claims3

Dependent claims

An AB Cascode input circuit, comprising:

a first current source having first and second terminals, said first terminal of said first current source being coupled to a first supply voltage source;
a second current source having first and second terminals, said first terminal of said second current source being coupled to said first supply voltage source;
a third current source having first and second terminals, said first terminal of said third current source being coupled to said first supply voltage source;
a fourth current source having first and second terminals, said first terminals of said fourth current source being coupled to a second supply voltage source;
a fifth current source having first and second terminals, said first terminals of said fifth current source being coupled to said second supply voltage source;
a first transistor having a source terminal coupled to said first current source, a gate terminal coupled to receive a first input signal and a drain terminal coupled to said second terminal of said fourth current source;
a second transistor having a source terminal coupled to said first current source, a gate terminal coupled to receive a second input signal and a drain terminal coupled to said second terminal of said fifth current source;
a first level converter having first and second terminals, said first terminal of said first level converter coupled to said second terminal of said fourth current source, said second terminal of said first level converter coupled to said second terminal of said second current source;
a second level converter having first and second terminals, said first terminal of said second level converter coupled to said second terminal of said fifth current source, said second terminal of said second level converter coupled to said second terminal of said third current source;
a third transistor having a source terminal coupled to said first supply voltage source and a gate and a drain terminal coupled together;
a fourth transistor having a source terminal coupled to said first supply voltage source and a gate coupled to said gate terminal of said third transistor and a drain terminal;
a fifth transistor having a source terminal coupled to said second terminal of said fifth current source, a gate terminal coupled to said first terminal of said first level converter, and a drain terminal coupled to said drain terminal of said third transistor;
and
a sixth transistor having a source terminal coupled to said second terminal of said fourth current source, a gate terminal coupled to said first terminal of said second level converter, and a drain terminal coupled to said drain terminal of said fourth transistor.

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Dependencies are inferred from the claim text.

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Abstract

An AB Cascode input circuit, comprising:

a first current source having first and second terminals, said first terminal of said first current source being coupled to a first supply voltage source;
a second current source having first and second terminals, said first terminal of said second current source being coupled to said first supply voltage source;
a third current source having first and second terminals, said first terminal of said third current source being coupled to said first supply voltage source;
a fourth current source having first and second terminals, said first terminals of said fourth current source being coupled to a second supply voltage source;
a fifth current source having first and second terminals, said first terminals of said fifth current source being coupled to said second supply voltage source;
a first transistor having a source terminal coupled to said first current source, a gate terminal coupled to receive a first input signal and a drain terminal coupled to said second terminal of said fourth current source;
a second transistor having a source terminal coupled to said first current source, a gate terminal coupled to receive a second input signal and a drain terminal coupled to said second terminal of said fifth current source;
a first level converter having first and second terminals, said first terminal of said first level converter coupled to said second terminal of said fourth current source, said second terminal of said first level converter coupled to said second terminal of said second current source;
a second level converter having first and second terminals, said first terminal of said second level converter coupled to said second terminal of said fifth current source, said second terminal of said second level converter coupled to said second terminal of said third current source;
a third transistor having a source terminal coupled to said first supply voltage source and a gate and a drain terminal coupled together;
a fourth transistor having a source terminal coupled to said first supply voltage source and a gate coupled to said gate terminal of said third transistor and a drain terminal;
a fifth transistor having a source terminal coupled to said second terminal of said fifth current source, a gate terminal coupled to said first terminal of said first level converter, and a drain terminal coupled to said drain terminal of said third transistor;
and
a sixth transistor having a source terminal coupled to said second terminal of said fourth current source, a gate terminal coupled to said first terminal of said second level converter, and a drain terminal coupled to said drain terminal of said fourth transistor.

11 more elements