Logarithmic amplifying circuit using quadritail cells

A logarithmic amplifying circuit comprising:

• a plurality of cascade-connected differential amplifiers;
• a plurality of rectifiers for receiving a differential input signal of a differential amplifier of each stage and a differential output signal of a differential amplifier of the last stage, respectively, and outputting differential currents corresponding to respective received input signals;
• an adder for adding a differential current of each of said rectifiers and outputting a signal corresponding to the sum thus obtained;
• and
• a neutral circuit provided for every one of said rectifiers which generates a neutral point voltage with reference to differential input signals of said corresponding rectifier;
• wherein said rectifiers each comprise a quadritail cell composed of a single tail current source and four bipolar transistors whose emitters are connected to said tail current source;
• bases of a first bipolar transistor and a second bipolar transistor of said quadrltail cell being connected to a respective terminals of a differential input pair of said rectifier, collectors of said first and second bipolar transistors being connected in common to one output terminal of said rectifier, collectors of a third and fourth bipolar transistors of said quadritail cell being connected in common to the other output terminal of said rectifier, and bases of said third and fourth bipolar transistors being connected in common to a line which is further connected to an output of said neutral circuit.

A logarithmic amplifying circuit, comprising:

• a plurality of cascade-connected differential amplifiers;
• a plurality of rectifiers for receiving a differential input signal of a differential amplifier of each stage and a differential output signal of a differential amplifier of the last stage, respectively, and outputting differential currents corresponding to respective received input signals;
• an adder for adding a differential current of each of said rectifiers and outputting a signal corresponding to the sum thus obtained;
• and
• a neutral circuit provided for every one of said rectifiers which generates a neutral point voltage with reference to differential input signals of said corresponding rectifier;
• wherein said rectifiers each comprise a quadritail cell composed of a single tail current source and four MOS transistors whose sources are connected to said tail current source;
• gates of a first MOS transistor and a second MOS transistor of said quadritail cell being connected to respective terminals of a differential input pair of said rectifier, drains of said first and second MOS transistors being connected in common to one output terminal of said rectifier, drains of a third and fourth MOS transistors of said quadritail cell being connected in common to the other output terminal of said rectifier, and gates of said third and fourth MOS transistors being connected in common to a line which is further connected to an output of said neutral circuit.