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US 5,471,161 AGranted
Circuit for calculating the minimum value
AssigneesYozan Inc., Sharp Kabushiki Kaisha
InventorsGuoliang Shou, Weikang Yang, Wiwat Wongwarawipat, Sunao Takatori, Makoto Yamamoto
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Abstract
A circuit calculating the minimum value comprising a plural number of pMOS, wherein source of the plural pMOS are connected to a power source with lower voltage than a drain, the drain is grounded through high resistance, in input voltage is connected to each pMOS, and a common output is connected to a drain of each pMOS.
Claims1
A circuit for outputting a minimum voltage of one of a plurality of inputs comprising:
- a common output;
- a resistance having a first terminal which is grounded and a second terminal;
- and
- a plurality of pMOS transistors, wherein each one of said plurality of pMOS transistors corresponds to one of said plurality of inputs, and wherein each said pMOS transistor comprises:
- a transistor source connected to a common power source;
- a transistor drain connected to said second terminal and to said common output;
- and
- a transistor gate connected to said corresponding one of said plurality of inputs;
- and
- wherein one of said plurality of transistors that receives a minimum voltage of said plurality of inputs conducts, causing said minimum input voltage to be applied to said drain of each remaining transistor so that each remaining transistor becomes non-conductive because each gate voltage becomes higher than a drain voltage for each remaining transistor, and wherein said pMOS transistors are connected within said circuit such that a minimal amount of current is drawn therethrough.
7 more elements
Dependencies are inferred from the claim text.