Setup or hold violation triggering

A circuit for producing a trigger signal when a data signal makes a transition between logic states at a time that violates set up or hold time requirements relative to an active edge of a clock signal, the circuit comprising:

• means (14,14') for generating a window pulse when the data signal undergoes a transition in logic state, the window pulse having a duration of a first time interval, the first time interval corresponding to the sum of a set up time requirement and a hold time requirement;
• means (28) for delaying an active edge of the clock signal for a second time interval, the second time interval corresponding to the hold time requirement;
• means for applying the window pulse to a data input of a bit storage means (20);
• means for clocking the bit storage means (20) with the delayed active edge of the clock signal, the bit storage means (20) thereby producing the output trigger pulse if the first pulse was active when the clocking occurred;
• and
• means (22) for resetting the bit storage means with a delayed version of the output trigger pulse to terminate the output pulse after a third time interval.

A method for producing a trigger signal when a data signal makes a transition between logic states at a time that violates set up or hold time requirements relative to an active edge of a clock signal, the method comprising the steps of:

• starting an active period of a first pulse when a transition in the data signal occurs, the first pulse having a duration corresponding to a set up time requirement;
• producing a set up time violation signal if an active clock edge occurs during the active period of the first pulse;
• commencing an active period of a second pulse when the active clock edge occurs, the second pulse having a duration corresponding to a hold time requirement;
• producing a hold time violation signal if a transition in the data signal occurs during the active period of the second pulse;
• and
• ORing the set up time violation signal and the hold time violation signal to create a trigger signal indicative of a set up time violation or a hold time violation.

A circuit for producing a trigger signal when a data signal makes a transition between logic states at a time that violates set up or hold time requirements relative to an active edge of a clock signal, the circuit comprising:

• means (46) for starting an active period of a first pulse when a transition in the data signal occurs, the first pulse having a duration corresponding to a set up time requirement;
• means (52) for producing a set up time violation signal if an active clock edge occurs during the active period of the first pulse;
• means (48) for commencing an active period of a second pulse when the active clock edge occurs, the second pulse having a duration corresponding to a hold time requirement;
• means (54) for producing a hold time violation signal if a transition in the data signal occurs during the active period of the second pulse;
• and
• means (56) for ORing the set up time violation signal and the hold time violation signal to create a trigger signal indicative of a set up time violation or a hold time violation.