Pre-charge triggering to increase throughput by initiating register output at beginning of pre-charge phase

A pre-charge triggered digital device that is characterized by an active phase and a pre-charge phase, with the end of the active phase and the beginning of the pre-charge phase being indicated by a PRECHARGE signal, comprising:

• input logic that receives and stores input data prior to being triggered;
• and
• function logic that processes input data received from said input logic during the active phase, at least a portion of such function logic being pre-charged;
• said input logic being triggered by said PRECHARGE signal to make the input data available to said function logic, said pre-charge phase ending at the beginning of the next clock cycle;
• wherein said pre-charged portions of said function logic are disabled from receiving input data from said input logic until the end of the precharge phase, and wherein said input logic is triggered by said PRECHARGE signal to make the stored input data available to said function logic, such that throughput is increased by the overlap of portions of the pre-charge phase with the delay through the input logic.

A pre-charge triggered digital device that is characterized by an active phase and a pre-charge phase, with the end of the active phase and the beginning of the pre-charge phase being indicated by a PRECHARGE signal, comprising:

• input logic that receives and stores input data prior to being triggered;
• and
• function logic that processes input data received from said input logic during the active phase, at least a portion of such function logic being pre-charged;
• said input logic being triggered by said PRECHARGE signal to make the input data available to said function logic, said pre-charge phase ending at the beginning of the next clock cycle;
• wherein said function logic includes pre-charge control logic for generating the PRECHARGE signal.

A pre-charge triggered digital device that is characterized by an active phase and a pre-charge phase, with the end Of the active phase and the beginning of the pre-charge phase being indicated by a PRECHARGE signal, comprising:

• input logic that receives and stores input data prior to being triggered;
• and
• function logic that processes input data received from said input logic during the active phase, at least a portion of such function logic being pre-charged;
• said input logic being triggered by said PRECHARGE signal to make the input data available to said function logic, said pre-charge phase ending at the beginning of the next clock cycle;
• wherein the input logic comprises an input register that passes data from a master latch through a slave latch to the register output when triggered either at the beginning of the next clock cycle or by the PRECHARGE signal.

A pre-charge triggering method for a pre-charged functional stage in which a PRECHARGE signal indicates the end of an active phase and the beginning of a pre-charge phase, and in which the functional stage includes input logic followed by non-pre-charged front-end logic and pre-charged function logic, with the input logic being triggerable during each clock cycle to make input data available to the front-end logic, comprising the steps:

• presenting input data to the input logic in preparation for the beginning of the next clock cycle;
• prior to the beginning of the next clock cycle, triggering the input logic using the PRECHARGE signal;
• and then
• passing the input data from the input logic to the front-end logic to initiate a new active phase prior to end of the pre-charge phase for the pre-charged logic;
• thereby hiding at least a portion of the pre-charge phase in the propagation delay through the front-end logic.

A pre-charge triggered functional stage in which a PRECHARGE signal indicates the end of an active phase and the beginning of a pre-charge phase, comprising:

• input logic that receives and stores input data prior to being triggered;
• non-pre-charged front-end logic that processes input data from said input logic at the beginning of an active phase;
• pre-charged function logic that processes data received from said front-end logic during the active phase;
• said input logic being triggered by said PRECHARGE signal to transfer the input data to said non-pre-charged front-end logic;
• thereby hiding at least a portion of the pre-charge phase in the propagation delay through the front-end logic.

A synchronous pipeline system including multiple pre-charged pipeline stages in which a PRECHARGE signal indicates the end of an active phase and the beginning of a pre-charge phase, with each pre-charged pipeline stage comprising:

• input logic that receives and stores input data prior to being triggered;
• function logic, at least a portion of which is precharged, that processes data received from said input logic at the beginning of an active phase;
• said input logic being triggered by said PRECHARGE signal to make input data available to said function logic;
• wherein, for at least one of said precharged pipeline stages, said function logic comprises:
• non-pre-charged front-end logic that processes input data from said input logic at the beginning of an active phase;
• and
• pre-charged function logic that processes data received from said front-end logic during the active phase;
• said input logic being triggered by said PRECHARGE signal to transfer the input data to said non-pre-charged front-end logic;
• thereby hiding at least a portion of the pre-charge phase in the propagation delay through the front-end logic.