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US 5,471,155 AGranted
User programmable product term width expander
AssigneeIntel Corporation
InventorRandy C. Steele
Life of this patent
Estimating the term…
Abstract
A product term allocation arrangement in which each of a first plurality of input conductors may be programmably joined to a first plurality of output conductors and to a first plurality of AND gates, a second plurality of input conductors may be programmably joined to a second plurality of output conductors and to a second plurality of AND gates, apparatus which may be selected to perform either an AND or an OR function connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates, and a plurality of OR gates connected to receive input signals from a selected number of the apparatus connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates.
Claims39
A programmable logic circuit comprising:
- (a) a plurality of sets of first conductors;
- (b) a plurality of sets of second conductors;
- (c) a plurality of sets of programmable devices, each set of the plurality of sets of programmable devices coupled to a corresponding set of the plurality of sets of first conductors and coupled to a corresponding set of the plurality of sets of second conductors for selectively coupling the corresponding set of the plurality of sets of first conductors to the corresponding set of the plurality of sets of second conductors,
- wherein each set of the plurality of sets of first conductors is coupled to only one set of programmable devices and wherein each set of the plurality of sets of second conductors is coupled to only one set of programmable devices;
- (d) a plurality of sets of AND gates, each set of the plurality of sets of AND gates coupled to a corresponding set of the plurality of sets of second conductors and each AND gate of the plurality of sets of AND gates for outputting a first output signal;
- and
- (e) at least one multiple-function gate, each of the at least one multiple-function gate coupled to receive the first output signal from at least two corresponding AND gates of the plurality of sets of AND gates for performing a selected function using the first output signal from the at least two corresponding AND gates to produce a second output signal.
4 more elements
A computer system comprising:
- (a) a processor;
- (b) a memory coupled to the processor;
- and
- (c) a programmable logic circuit coupled to the processor, the programmable logic circuit comprising:
- (i) a plurality of sets of first conductors,
- (ii) a plurality of sets of second conductors,
- (iii) a plurality of sets of programmable devices, each set of the plurality of sets of programmable devices coupled to a corresponding set of the plurality of sets of first conductors and coupled to a corresponding set of the plurality of sets of second conductors for selectively coupling the corresponding set of the plurality of sets of first conductors to the corresponding set of the plurality of sets of second conductors,
- wherein each set of the plurality of sets of first conductors is coupled to only one set of programmable devices and wherein each set of the plurality of sets of second conductors is coupled to only one set of programmable devices,
- (iv) a plurality of sets of AND gates, each set of the plurality of sets of AND gates coupled to a corresponding set of the plurality of sets of second conductors and each AND gate of the plurality of sets of AND gates for outputting a first output signal, and
- (v) at least one multiple-function gate, each of the at least one multiple-function gate coupled to receive the first output signal from at least two corresponding AND gates of the plurality of sets of AND gates for performing a selected function using the first output signal from the at least two corresponding AND gates to produce a second output signal.
7 more elements
A programmable logic circuit comprising:
- (a) a plurality of sets of first conductors;
- (b) a plurality of sets of second conductors;
- (c) a plurality of sets of programmable means, each set of the plurality of sets of programmable means coupled to a corresponding set of the plurality of sets of first conductors and coupled to a corresponding set of the plurality of sets of second conductors for selectively coupling the corresponding set of the plurality of sets of first conductors to the corresponding set of the plurality of sets of second conductors,
- wherein each set of the plurality of sets of first conductors is coupled to only one set of programmable means and wherein each set of the plurality of sets of second conductors is coupled to only one set of programmable means;
- (d) a plurality of sets of AND means, each set of the plurality of sets of AND means coupled to a corresponding set of the plurality of sets of second conductors and each AND means of the plurality of sets of AND means for outputting a first output signal;
- and
- (e) at least one multiple-function means, each of the at least one multiple-function means coupled to receive the first output signal from at least two corresponding AND means of the plurality of sets of AND means for performing a selected function using the first output signal from the at least two corresponding AND means to produce a second output signal.
4 more elements
A computer system comprising:
- (a) a processor;
- (b) a memory coupled to the processor;
- and
- (c) a programmable logic circuit coupled to the processor, the programmable logic circuit comprising:
- (i) a plurality of sets of first conductors,
- (ii) a plurality of sets of second conductors,
- (iii) a plurality of sets of programmable means, each set of the plurality of sets of programmable means coupled to a corresponding set of the plurality of sets of first conductors and coupled to a corresponding set of the plurality of sets of second conductors for selectively coupling the corresponding set of the plurality of sets of first conductors to the corresponding set of the plurality of sets of second conductors,
- wherein each set of the plurality of sets of first conductors is coupled to only one set of programmable means and wherein each set of the plurality of sets of second conductors is coupled to only one set of programmable means,
- (iv) a plurality of sets of AND means, each set of the plurality of sets of AND means coupled to a corresponding set of the plurality of sets of second conductors and each AND means of the plurality of sets of AND means for outputting a first output signal, and
- (v) at least one multiple-function means, each of the at least one multiple-function means coupled to receive the first output signal from at least two corresponding AND means of the plurality of sets of AND means for performing a selected function using the first output signal from the at least two corresponding AND means to produce a second output signal.
7 more elements
A programmable logic circuit comprising:
- (a) a plurality of first conductors;
- (b) a plurality of second conductors;
- (c) a plurality of programmable devices, each of the plurality of programmable devices coupled to a corresponding one of the plurality of first conductors and coupled to a corresponding one of the plurality of second conductors for selectively coupling the corresponding one first conductor to the corresponding one second conductor;
- (d) a plurality of AND gates coupled to the plurality of second conductors, each AND gate of the plurality of AND gates for outputting a first output signal;
- (e) a plurality of multiple-function gates, each of the plurality of multiple-function gates coupled to receive the first output signal from at least two corresponding AND gates of the plurality of AND gates for performing a selected function using the first output signal from the at least two corresponding AND gates to produce a second output signal;
- (f) a plurality of OR gates, each OR gate of the plurality of OR gates for receiving the second output signal from at least two corresponding multiple-function gates of the plurality of multiple-function gates to produce a third output signal;
- and
- (g) a plurality of switches coupled between the plurality of multiple-function gates and the plurality of OR gates, each switch of the plurality of switches for coupling the second output signal from a corresponding one of the plurality of multiple-function gates to one of the plurality of OR gates.
5 more elements
A computer system comprising:
- (a) a processor;
- (b) a memory coupled to the processor;
- and
- (c) a programmable logic circuit coupled to the processor, the programmable logic circuit comprising:
- (i) a plurality of first conductors,
- (ii) a plurality of second conductors,
- (iii) a plurality of programmable devices, each of the plurality of programmable devices coupled to a corresponding one of the plurality of first conductors and coupled to a corresponding one of the plurality of second conductors for selectively coupling the corresponding one first conductor to the corresponding one second conductor,
- (iv) a plurality of AND gates coupled to the plurality of second conductors, each AND gate of the plurality of AND gates for outputting a first output signal,
- (v) a plurality of multiple-function gates, each of the plurality of multiple-function gates coupled to receive the first output signal from at least two corresponding AND gates of the plurality of AND gates for performing a selected function using the first output signal from the at least two corresponding AND gates to produce a second output signal,
- (vi) a plurality of OR gates, each OR gate of the plurality of OR gates for receiving the second output signal from at least two corresponding multiple-function gates of the plurality of multiple-function gates to produce a third output signal, and
- (vii) a plurality of switches coupled between the plurality of multiple-function gates and the plurality of OR gates, each switch of the plurality of switches for coupling the second output signal from a corresponding one of the plurality of multiple-function gates to one of the plurality of OR gates.
8 more elements
Dependencies are inferred from the claim text.