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US 5,471,150 AGranted
Buffer with high and low speed input buffers
AssigneeSamsung Electronics Co., Ltd.
InventorsChil-min Jung, Kyeong-rae Kim, Jeong-hee Lee
Life of this patent
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Abstract
An input buffer includes a low-speed input buffer for buffering an input signal at the time of low-speed operation, a high-speed input buffer being controlled by the low-speed input buffer, for adjusting the high-level and low-level logic of an input signal at the time of high-speed operation and an output driver for outputting high-level or low-level logic by inputting the output signal of the high-speed input buffer. Therefore, there is no direct current present, the operational speed is increased and noise can be reduced.
Claims21
An input buffer comprising:
- a low-speed input buffer receiving an input signal and generating a buffered output signal during low-speed operation;
- a high-speed, logically high input buffer controlled by the low-speed input buffer, receiving the input signal, and generating a logically high output signal during high-speed operation;
- a high-speed, logically low input buffer controlled by the low-speed input buffer, receiving the input signal, and generating a logically low output signal during high-speed operation;
- and
- an output driver exclusively receiving the logically high output signal and the logically low output signal, and generating an output signal in response thereto.
2 more elements
An input buffer comprising:
- a low-speed input buffer receiving an input signal, generating a buffered output signal during low-speed operation, and comprising;
- a first inverter receiving the input signal and inverting the input signal;
- a first pull-up transistor having a gate electrode connected to the inverted output of the first inverter, a source electrode connected to a power voltage, and a drain electrode;
- and
- a first pull-down transistor having a gate electrode connected to the inverted output of the first inverter, a source electrode connected to ground, and a drain electrode connected to the drain electrode of the first pull-up transistor;
- a high-speed, logically high input buffer controlled by the low-speed input buffer, receiving the input signal, generating a logically high output signal during high-speed operation, and comprising;
- second and third inverters receiving the input signal;
- a second pull-up transistor having a source electrode connected to the power voltage, a gate electrode receiving the input signal, and a drain electrode;
- a second pull-down transistor having a drain electrode connected to the drain electrode of the second pull-up transistor, a gate electrode receiving the input signal, and a source electrode connected to an output of the third inverter;
- a capacitor connected across the output of the third inverter and ground;
- and
- a first pass transistor having a gate electrode connected to the output of the first inverter, a source electrode connected to the output of the third inverter, and a drain electrode connected to the drain electrode of the second pull-up transistor;
- a high-speed, logically low input buffer controlled by the low-speed input buffer, receiving the input signal, and generating a logically low output signal during high-speed operation;
- and
- an output driver at which the output of the high-speed, logically high input buffer, and the output of the high-speed, logically low input buffer are apparent.
12 more elements
An input buffer comprising:
- a low-speed input buffer receiving an input signal during low-speed operation;
- a high-speed input buffer, controlled by the low-speed input buffer, adjusting high-level and low-level logic of the input signal during high-speed operation, and providing the adjusted input signal as an output;
- and
- an output driver, exclusively receiving the adjusted input signal, and generating high-level and low-level logic signals in response to the output of the high-speed input buffer.
1 more element
An input buffer comprising:
- a low-speed input buffer receiving an input signal during low-speed operation, and comprising;
- a first inverter receiving inverting the input signal;
- a first pull-up transistor having a gate electrode connected to the output of the first inverter, a source electrode connected to a power voltage, and a drain electrode;
- and
- a first pull-down transistor having a gate electrode connected to the output of the first inverter, a source electrode connected to ground potential, and a drain electrode connected to the drain electrode of the first pull-up transistor;
- a high-speed input buffer, controlled by the low-speed input buffer, adjusting high-level and low-level logic of the input signal during high-speed operation, providing the adjusted input signal as an output, and comprising;
- high-level logic adjusting means for adjusting a high-level logic value for the input signal;
- and
- low-level logic adjusting means for adjusting a low-level logic value for the input signal, wherein the high-level logic adjusting means further comprises;
- second and third inverters receiving the input signal;
- a second pull-up transistor having a source electrode connected to a power voltage, a gate electrode receiving the input signal, and a drain electrode;
- a second pull-down transistor having a drain electrode connected to the drain electrode of the second pull-up transistor, a gate electrode receiving the input signal, and a source electrode connected to the output of the third inverter;
- a capacitor connected across the output of the third inverter and ground;
- and
- a first pass transistor having a gate electrode connected to the output of the first inverter, a source electrode connected to the output of the third inverter, and a drain electrode connected to the drain electrode of the second pull-up transistor;
- an output driver generating the high-level and low-level logic signals in response to the output of the high-speed input buffer.
13 more elements
Dependencies are inferred from the claim text.